diff options
Diffstat (limited to 'VexRiscv/src/test/cpp/raw/pmp')
| -rw-r--r-- | VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm | 258 | ||||
| -rwxr-xr-x | VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf | bin | 0 -> 5776 bytes | |||
| -rw-r--r-- | VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex | 58 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/raw/pmp/build/pmp.map | 35 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/raw/pmp/makefile | 3 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/raw/pmp/src/crt.S | 269 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/raw/pmp/src/ld | 16 |
7 files changed, 639 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm new file mode 100644 index 0000000..f8a30e2 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm @@ -0,0 +1,258 @@ + +build/pmp.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00000493 li s1,0 +80000004: 00000097 auipc ra,0x0 +80000008: 01008093 addi ra,ra,16 # 80000014 <trap> +8000000c: 30509073 csrw mtvec,ra +80000010: 0140006f j 80000024 <test0> + +80000014 <trap>: +80000014: 341f1073 csrw mepc,t5 +80000018: 00049463 bnez s1,80000020 <trap_exit> +8000001c: 30200073 mret + +80000020 <trap_exit>: +80000020: 000f0067 jr t5 + +80000024 <test0>: +80000024: 00000e13 li t3,0 +80000028: 00000f17 auipc t5,0x0 +8000002c: 324f0f13 addi t5,t5,804 # 8000034c <fail> +80000030: 800000b7 lui ra,0x80000 +80000034: 80008237 lui tp,0x80008 +80000038: deadc137 lui sp,0xdeadc +8000003c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +80000040: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffca8> +80000044: 00222023 sw sp,0(tp) # 80008000 <pass+0x7ca8> +80000048: 0000a183 lw gp,0(ra) +8000004c: 30311063 bne sp,gp,8000034c <fail> +80000050: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> +80000054: 2e311c63 bne sp,gp,8000034c <fail> +80000058: 071a02b7 lui t0,0x71a0 +8000005c: 3a029073 csrw pmpcfg0,t0 +80000060: 3a002373 csrr t1,pmpcfg0 +80000064: 2e629463 bne t0,t1,8000034c <fail> +80000068: 1a1902b7 lui t0,0x1a190 +8000006c: 30428293 addi t0,t0,772 # 1a190304 <_start-0x65e6fcfc> +80000070: 3a129073 csrw pmpcfg1,t0 +80000074: 000f12b7 lui t0,0xf1 +80000078: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6> +8000007c: 3a229073 csrw pmpcfg2,t0 +80000080: 3a202373 csrr t1,pmpcfg2 +80000084: 2c629463 bne t0,t1,8000034c <fail> +80000088: 1c1e22b7 lui t0,0x1c1e2 +8000008c: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700> +80000090: 3a329073 csrw pmpcfg3,t0 +80000094: 200002b7 lui t0,0x20000 +80000098: 3b029073 csrw pmpaddr0,t0 +8000009c: 3b002373 csrr t1,pmpaddr0 +800000a0: 2a629663 bne t0,t1,8000034c <fail> +800000a4: fff00293 li t0,-1 +800000a8: 3b129073 csrw pmpaddr1,t0 +800000ac: 202002b7 lui t0,0x20200 +800000b0: 3b229073 csrw pmpaddr2,t0 +800000b4: 200042b7 lui t0,0x20004 +800000b8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000bc: 3b329073 csrw pmpaddr3,t0 +800000c0: 200042b7 lui t0,0x20004 +800000c4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000c8: 3b429073 csrw pmpaddr4,t0 +800000cc: 200042b7 lui t0,0x20004 +800000d0: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000d4: 3b529073 csrw pmpaddr5,t0 +800000d8: 230002b7 lui t0,0x23000 +800000dc: fff28293 addi t0,t0,-1 # 22ffffff <_start-0x5d000001> +800000e0: 3b629073 csrw pmpaddr6,t0 +800000e4: 220402b7 lui t0,0x22040 +800000e8: fff28293 addi t0,t0,-1 # 2203ffff <_start-0x5dfc0001> +800000ec: 3b729073 csrw pmpaddr7,t0 +800000f0: 200d02b7 lui t0,0x200d0 +800000f4: 3b829073 csrw pmpaddr8,t0 +800000f8: 200e02b7 lui t0,0x200e0 +800000fc: 3b929073 csrw pmpaddr9,t0 +80000100: fff00293 li t0,-1 +80000104: 3ba29073 csrw pmpaddr10,t0 +80000108: 00000293 li t0,0 +8000010c: 3bb29073 csrw pmpaddr11,t0 +80000110: 00000293 li t0,0 +80000114: 3bc29073 csrw pmpaddr12,t0 +80000118: 00000293 li t0,0 +8000011c: 3bd29073 csrw pmpaddr13,t0 +80000120: 00000293 li t0,0 +80000124: 3be29073 csrw pmpaddr14,t0 +80000128: fff00293 li t0,-1 +8000012c: 3bf29073 csrw pmpaddr15,t0 +80000130: 00c10137 lui sp,0xc10 +80000134: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012> +80000138: 0020a023 sw sp,0(ra) +8000013c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000> +80000140: 0000a183 lw gp,0(ra) +80000144: 20311463 bne sp,gp,8000034c <fail> +80000148: 00000193 li gp,0 +8000014c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> +80000150: 1e311e63 bne sp,gp,8000034c <fail> + +80000154 <test1>: +80000154: 00100e13 li t3,1 +80000158: 00000f17 auipc t5,0x0 +8000015c: 1f4f0f13 addi t5,t5,500 # 8000034c <fail> +80000160: 079a12b7 lui t0,0x79a1 +80000164: 80828293 addi t0,t0,-2040 # 79a0808 <_start-0x7865f7f8> +80000168: 3a029073 csrw pmpcfg0,t0 +8000016c: 3a002373 csrr t1,pmpcfg0 +80000170: 1c629e63 bne t0,t1,8000034c <fail> +80000174: 808000b7 lui ra,0x80800 +80000178: deadc137 lui sp,0xdeadc +8000017c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +80000180: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8> +80000184: 00000f17 auipc t5,0x0 +80000188: 010f0f13 addi t5,t5,16 # 80000194 <test2> +8000018c: 0000a183 lw gp,0(ra) +80000190: 1bc0006f j 8000034c <fail> + +80000194 <test2>: +80000194: 00200e13 li t3,2 +80000198: 00000f17 auipc t5,0x0 +8000019c: 1b4f0f13 addi t5,t5,436 # 8000034c <fail> +800001a0: 071a02b7 lui t0,0x71a0 +800001a4: 3a029073 csrw pmpcfg0,t0 +800001a8: 3a002373 csrr t1,pmpcfg0 +800001ac: 1a628063 beq t0,t1,8000034c <fail> +800001b0: 3b305073 csrwi pmpaddr3,0 +800001b4: 3b302373 csrr t1,pmpaddr3 +800001b8: 18031a63 bnez t1,8000034c <fail> +800001bc: 3b205073 csrwi pmpaddr2,0 +800001c0: 3b202373 csrr t1,pmpaddr2 +800001c4: 18030463 beqz t1,8000034c <fail> +800001c8: 808000b7 lui ra,0x80800 +800001cc: deadc137 lui sp,0xdeadc +800001d0: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +800001d4: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8> +800001d8: 00000f17 auipc t5,0x0 +800001dc: 010f0f13 addi t5,t5,16 # 800001e8 <test3> +800001e0: 0000a183 lw gp,0(ra) +800001e4: 1680006f j 8000034c <fail> + +800001e8 <test3>: +800001e8: 00300e13 li t3,3 +800001ec: 00000f17 auipc t5,0x0 +800001f0: 160f0f13 addi t5,t5,352 # 8000034c <fail> +800001f4: 00ff02b7 lui t0,0xff0 +800001f8: 3b32a073 csrs pmpaddr3,t0 +800001fc: 3b302373 csrr t1,pmpaddr3 +80000200: 14629663 bne t0,t1,8000034c <fail> +80000204: 0ff00293 li t0,255 +80000208: 3b32a073 csrs pmpaddr3,t0 +8000020c: 3b302373 csrr t1,pmpaddr3 +80000210: 00ff02b7 lui t0,0xff0 +80000214: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> +80000218: 12629a63 bne t0,t1,8000034c <fail> +8000021c: 00ff02b7 lui t0,0xff0 +80000220: 3b32b073 csrc pmpaddr3,t0 +80000224: 3b302373 csrr t1,pmpaddr3 +80000228: 0ff00293 li t0,255 +8000022c: 12629063 bne t0,t1,8000034c <fail> +80000230: 00ff02b7 lui t0,0xff0 +80000234: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> +80000238: 3a02b073 csrc pmpcfg0,t0 +8000023c: 3a002373 csrr t1,pmpcfg0 +80000240: 079a02b7 lui t0,0x79a0 +80000244: 10629463 bne t0,t1,8000034c <fail> +80000248: 00ff02b7 lui t0,0xff0 +8000024c: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9> +80000250: 3a02a073 csrs pmpcfg0,t0 +80000254: 3a002373 csrr t1,pmpcfg0 +80000258: 079a02b7 lui t0,0x79a0 +8000025c: 70728293 addi t0,t0,1799 # 79a0707 <_start-0x7865f8f9> +80000260: 0e629663 bne t0,t1,8000034c <fail> + +80000264 <test4>: +80000264: 00400e13 li t3,4 +80000268: 00000f17 auipc t5,0x0 +8000026c: 0e4f0f13 addi t5,t5,228 # 8000034c <fail> +80000270: 00000117 auipc sp,0x0 +80000274: 01010113 addi sp,sp,16 # 80000280 <test5> +80000278: 34111073 csrw mepc,sp +8000027c: 30200073 mret + +80000280 <test5>: +80000280: 00500e13 li t3,5 +80000284: 00000f17 auipc t5,0x0 +80000288: 0c8f0f13 addi t5,t5,200 # 8000034c <fail> +8000028c: deadc137 lui sp,0xdeadc +80000290: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +80000294: 808000b7 lui ra,0x80800 +80000298: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8> +8000029c: 00000f17 auipc t5,0x0 +800002a0: 010f0f13 addi t5,t5,16 # 800002ac <test6> +800002a4: 0000a183 lw gp,0(ra) +800002a8: 0a40006f j 8000034c <fail> + +800002ac <test6>: +800002ac: 00600e13 li t3,6 + +800002b0 <test7>: +800002b0: 00700e13 li t3,7 +800002b4: 00000f17 auipc t5,0x0 +800002b8: 098f0f13 addi t5,t5,152 # 8000034c <fail> +800002bc: 890000b7 lui ra,0x89000 +800002c0: ff008093 addi ra,ra,-16 # 88fffff0 <pass+0x8fffc98> +800002c4: 0000a183 lw gp,0(ra) +800002c8: 00000f17 auipc t5,0x0 +800002cc: 010f0f13 addi t5,t5,16 # 800002d8 <test8a> +800002d0: 0030a023 sw gp,0(ra) +800002d4: 0780006f j 8000034c <fail> + +800002d8 <test8a>: +800002d8: 00800e13 li t3,8 +800002dc: 00000f17 auipc t5,0x0 +800002e0: 014f0f13 addi t5,t5,20 # 800002f0 <test8b> +800002e4: 00100493 li s1,1 +800002e8: 3a305073 csrwi pmpcfg3,0 +800002ec: 0600006f j 8000034c <fail> + +800002f0 <test8b>: +800002f0: 00800e13 li t3,8 +800002f4: 1c1e22b7 lui t0,0x1c1e2 +800002f8: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700> +800002fc: 3a302373 csrr t1,pmpcfg3 +80000300: 04629663 bne t0,t1,8000034c <fail> + +80000304 <test9a>: +80000304: 00900e13 li t3,9 +80000308: 00000f17 auipc t5,0x0 +8000030c: 044f0f13 addi t5,t5,68 # 8000034c <fail> +80000310: 00000493 li s1,0 +80000314: 00000117 auipc sp,0x0 +80000318: 01010113 addi sp,sp,16 # 80000324 <test9b> +8000031c: 34111073 csrw mepc,sp +80000320: 30200073 mret + +80000324 <test9b>: +80000324: 00900e13 li t3,9 +80000328: 00000f17 auipc t5,0x0 +8000032c: 014f0f13 addi t5,t5,20 # 8000033c <test9c> +80000330: 00100493 li s1,1 +80000334: 3ba05073 csrwi pmpaddr10,0 +80000338: 0140006f j 8000034c <fail> + +8000033c <test9c>: +8000033c: 00900e13 li t3,9 +80000340: fff00293 li t0,-1 +80000344: 3ba02373 csrr t1,pmpaddr10 +80000348: 00628863 beq t0,t1,80000358 <pass> + +8000034c <fail>: +8000034c: f0100137 lui sp,0xf0100 +80000350: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffbcc> +80000354: 01c12023 sw t3,0(sp) + +80000358 <pass>: +80000358: f0100137 lui sp,0xf0100 +8000035c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffbc8> +80000360: 00012023 sw zero,0(sp) diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf Binary files differnew file mode 100755 index 0000000..f6c3c69 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex new file mode 100644 index 0000000..509c291 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex @@ -0,0 +1,58 @@ +:0200000480007A
+:10000000930400009700000093800001739050302B
+:100010006F00400173101F3463940400730020309C
+:1000200067000F00130E0000170F0000130F4F3270
+:10003000B70000803782008037C1ADDE1301F1EEDA
+:1000400023A020002320220083A100006310313070
+:1000500083210200631C312EB7021A077390023A03
+:100060007323003A6394622EB702191A93824230C6
+:100070007390123AB7120F009382A2907390223AB3
+:100080007323203A6394622CB7221E1C9382029041
+:100090007390323AB70200207390023B7323003B07
+:1000A0006396622A9302F0FF7390123BB7022020FE
+:1000B0007390223BB74200209382F2FF7390323B51
+:1000C000B74200209382F2FF7390423BB742002078
+:1000D0009382F2FF7390523BB70200239382F2FFA8
+:1000E0007390623BB70204229382F2FF7390723BDB
+:1000F000B7020D207390823BB7020E207390923BA3
+:100100009302F0FF7390A23B930200007390B23B06
+:10011000930200007390C23B930200007390D23BA5
+:10012000930200007390E23B9302F0FF7390F23B66
+:100130003701C1001301E1FE23A02000232022008B
+:1001400083A1000063143120930100008321020089
+:10015000631E311E130E1000170F0000130F4F1FE8
+:10016000B7129A07938282807390023A7323003AFF
+:10017000639E621CB700808037C1ADDE1301F1EED3
+:1001800023A02000170F0000130F0F0183A1000010
+:100190006F00C01B130E2000170F0000130F4F1B22
+:1001A000B7021A077390023A7323003A6380621A07
+:1001B0007350303B7323303B631A03187350203B5A
+:1001C0007323203B63040318B700808037C1ADDE82
+:1001D0001301F1EE23A02000170F0000130F0F01F1
+:1001E00083A100006F008016130E3000170F00006F
+:1001F000130F0F16B702FF0073A0323B7323303B7F
+:10020000639662149302F00F73A0323B7323303B6A
+:10021000B702FF009382F20F639A6212B702FF00E7
+:1002200073B0323B7323303B9302F00F6390621242
+:10023000B702FF009382F20F73B0023A7323003AC1
+:10024000B7029A0763946210B702FF00938272703C
+:1002500073A0023A7323003AB7029A07938272702E
+:100260006396620E130E4000170F0000130F4F0E1F
+:1002700017010000130101017310113473002030C5
+:10028000130E5000170F0000130F8F0C37C1ADDE97
+:100290001301F1EEB700808023A02000170F0000AB
+:1002A000130F0F0183A100006F00400A130E6000BE
+:1002B000130E7000170F0000130F8F09B70000898D
+:1002C000938000FF83A10000170F0000130F0F01A0
+:1002D00023A030006F008007130E8000170F00006E
+:1002E000130F4F01930410007350303A6F00000653
+:1002F000130E8000B7221E1C938202907323303AA3
+:1003000063966204130E9000170F0000130F4F0442
+:100310009304000017010000130101017310113450
+:1003200073002030130E9000170F0000130F4F01C1
+:10033000930410007350A03B6F004001130E900017
+:100340009302F0FF7323A03B63886200370110F033
+:10035000130141F22320C101370110F0130101F212
+:040360002320010055
+:040000058000000077
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.map b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.map new file mode 100644 index 0000000..ab2c78d --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.map @@ -0,0 +1,35 @@ + +Memory Configuration + +Name Origin Length Attributes +onChipRam 0x0000000080000000 0x0000000000020000 w !xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD build/src/crt.o +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a +START GROUP +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a +END GROUP +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a + +.crt_section 0x0000000080000000 0x364 + 0x0000000080000000 . = ALIGN (0x4) + *crt.o(.text) + .text 0x0000000080000000 0x364 build/src/crt.o + 0x0000000080000000 _start + 0x0000000080000014 trap +OUTPUT(build/pmp.elf elf32-littleriscv) + +.data 0x0000000080000364 0x0 + .data 0x0000000080000364 0x0 build/src/crt.o + +.bss 0x0000000080000364 0x0 + .bss 0x0000000080000364 0x0 build/src/crt.o + +.riscv.attributes + 0x0000000000000000 0x1a + .riscv.attributes + 0x0000000000000000 0x1a build/src/crt.o diff --git a/VexRiscv/src/test/cpp/raw/pmp/makefile b/VexRiscv/src/test/cpp/raw/pmp/makefile new file mode 100644 index 0000000..0069df4 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=pmp + +include ../common/asm.mk diff --git a/VexRiscv/src/test/cpp/raw/pmp/src/crt.S b/VexRiscv/src/test/cpp/raw/pmp/src/crt.S new file mode 100644 index 0000000..ce10ad7 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/src/crt.S @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se> + * + * SPDX-License-Identifier: MIT + */ + +#define TEST_ID x28 +#define TRAP_RETURN x30 +#define TRAP_EXIT x9 + +#define PMPCFG0 0x071a0000 +#define PMPCFG0_ 0x079a0808 +#define PMPCFG1 0x1a190304 +#define PMPCFG2 0x000f090a +#define PMPCFG3 0x1c1e1900 + +#define PMPADDR0 0x20000000 // OFF (test0) -> TOR (test1) -> OFF (test2) +#define PMPADDR1 0xffffffff // OFF (test0) -> TOR (test1) -> OFF (test2) +#define PMPADDR2 0x20200000 // NAPOT W +#define PMPADDR3 0x20003fff // OFF RWX -> 0x00000000 OFF RWX (test2) +#define PMPADDR4 0x20003fff // OFF X +#define PMPADDR5 0x20003fff // OFF RW +#define PMPADDR6 0x22ffffff // NAPOT R +#define PMPADDR7 0x2203ffff // NAPOT W +#define PMPADDR8 0x200d0000 // TOR W +#define PMPADDR9 0x200e0000 // TOR R +#define PMPADDR10 0xffffffff // TOR RWX +#define PMPADDR11 0x00000000 // OFF +#define PMPADDR12 0x00000000 // OFF +#define PMPADDR13 0x00000000 // NAPOT R +#define PMPADDR14 0x00000000 // NAPOT WX +#define PMPADDR15 0xffffffff // NAPOT X + +.global _start +_start: + li TRAP_EXIT, 0x0 + la x1, trap + csrw mtvec, x1 + j test0 + +.global trap +trap: + csrw mepc, TRAP_RETURN + bnez TRAP_EXIT, trap_exit + mret + +// return from trap, but stay in M-mode +trap_exit: + jr TRAP_RETURN + +// configure PMP, attempt read/write from machine mode +test0: + li TEST_ID, 0 + la TRAP_RETURN, fail + + li x1, 0x80000000 + li x4, 0x80008000 + li x2, 0xdeadbeef + sw x2, 0x0(x1) + sw x2, 0x0(x4) + lw x3, 0x0(x1) + bne x2, x3, fail + lw x3, 0x0(x4) + bne x2, x3, fail + + li x5, PMPCFG0 + csrw pmpcfg0, x5 + csrr x6, pmpcfg0 + bne x5, x6, fail + li x5, PMPCFG1 + csrw pmpcfg1, x5 + li x5, PMPCFG2 + csrw pmpcfg2, x5 + csrr x6, pmpcfg2 + bne x5, x6, fail + li x5, PMPCFG3 + csrw pmpcfg3, x5 + li x5, PMPADDR0 + csrw pmpaddr0, x5 + csrr x6, pmpaddr0 + bne x5, x6, fail + li x5, PMPADDR1 + csrw pmpaddr1, x5 + li x5, PMPADDR2 + csrw pmpaddr2, x5 + li x5, PMPADDR3 + csrw pmpaddr3, x5 + li x5, PMPADDR4 + csrw pmpaddr4, x5 + li x5, PMPADDR5 + csrw pmpaddr5, x5 + li x5, PMPADDR6 + csrw pmpaddr6, x5 + li x5, PMPADDR7 + csrw pmpaddr7, x5 + li x5, PMPADDR8 + csrw pmpaddr8, x5 + li x5, PMPADDR9 + csrw pmpaddr9, x5 + li x5, PMPADDR10 + csrw pmpaddr10, x5 + li x5, PMPADDR11 + csrw pmpaddr11, x5 + li x5, PMPADDR12 + csrw pmpaddr12, x5 + li x5, PMPADDR13 + csrw pmpaddr13, x5 + li x5, PMPADDR14 + csrw pmpaddr14, x5 + li x5, PMPADDR15 + csrw pmpaddr15, x5 + + li x2, 0xc0ffee + sw x2, 0x0(x1) + sw x2, 0x0(x4) + lw x3, 0x0(x1) + bne x2, x3, fail + li x3, 0x0 + lw x3, 0x0(x4) + bne x2, x3, fail + +// lock region 2, attempt read/write from machine mode +test1: + li TEST_ID, 1 + la TRAP_RETURN, fail + li x5, PMPCFG0_ + csrw pmpcfg0, x5 // lock region 2 + csrr x6, pmpcfg0 + bne x5, x6, fail + li x1, 0x80800000 + li x2, 0xdeadbeef + sw x2, 0x0(x1) // should be OK (write region 2) + la TRAP_RETURN, test2 + lw x3, 0x0(x1) // should fault (read region 2) + j fail + +// "unlock" region 2, attempt read/write from machine mode +test2: + li TEST_ID, 2 + la TRAP_RETURN, fail + li x5, PMPCFG0 + csrw pmpcfg0, x5 // "unlock" region 2 + csrr x6, pmpcfg0 + beq x5, x6, fail + csrwi pmpaddr3, 0x0 + csrr x6, pmpaddr3 + bnez x6, fail + csrwi pmpaddr2, 0x0 + csrr x6, pmpaddr2 + beqz x6, fail + li x1, 0x80800000 + li x2, 0xdeadbeef + sw x2, 0x0(x1) // should still be OK (write region 2) + la TRAP_RETURN, test3 + lw x3, 0x0(x1) // should still fault (read region 2) + j fail + +// verify masked CSR read/write operations +test3: + li TEST_ID, 3 + la TRAP_RETURN, fail + li x5, 0x00ff0000 + csrs pmpaddr3, x5 + csrr x6, pmpaddr3 + bne x5, x6, fail + li x5, 0x000000ff + csrs pmpaddr3, x5 + csrr x6, pmpaddr3 + li x5, 0x00ff00ff + bne x5, x6, fail + li x5, 0x00ff0000 + csrc pmpaddr3, x5 + csrr x6, pmpaddr3 + li x5, 0x000000ff + bne x5, x6, fail + li x5, 0x00ff00ff + csrc pmpcfg0, x5 + csrr x6, pmpcfg0 + li x5, 0x079a0000 + bne x5, x6, fail + li x5, 0x00ff0707 + csrs pmpcfg0, x5 + csrr x6, pmpcfg0 + li x5, 0x079a0707 + bne x5, x6, fail + +// jump into U-mode +test4: + li TEST_ID, 4 + la TRAP_RETURN, fail + la x2, test5 + csrw mepc, x2 + mret + +// attempt to read/write the locked region from U-mode +test5: + li TEST_ID, 5 + la TRAP_RETURN, fail + li x2, 0xdeadbeef + li x1, 0x80800000 + sw x2, 0x0(x1) // should be OK (write region 2) + la TRAP_RETURN, test6 + lw x3, 0x0(x1) // should fault (read region 2) + j fail + +// attempt to read/write overlapping regions from U-mode +test6: + li TEST_ID, 6 + //la TRAP_RETURN, fail + //li x2, 0xdeadbeef + //li x1, 0x88000000 + //sw x2, 0x0(x1) // should be OK (write region 6/7) + //lw x3, 0x0(x1) // should be OK (write region 6/7) + +test7: + li TEST_ID, 7 + la TRAP_RETURN, fail + li x1, 0x88fffff0 + lw x3, 0x0(x1) // should be OK (read region 6) + la TRAP_RETURN, test8a + sw x3, 0x0(x1) // should fault (write region 6) + j fail + +// attempt to write a pmpcfg# register from U-mode +test8a: + li TEST_ID, 8 + la TRAP_RETURN, test8b + li TRAP_EXIT, 0x1 + csrwi pmpcfg3, 0x0 + j fail + +// check the result from M-mode +test8b: + li TEST_ID, 8 + li x5, PMPCFG3 + csrr x6, pmpcfg3 + bne x5, x6, fail + +// jump back into U-mode +test9a: + li TEST_ID, 9 + la TRAP_RETURN, fail + li TRAP_EXIT, 0x0 + la x2, test9b + csrw mepc, x2 + mret + +// attempt to write a pmpaddr# register from U-mode +test9b: + li TEST_ID, 9 + la TRAP_RETURN, test9c + li TRAP_EXIT, 0x1 + csrwi pmpaddr10, 0x0 + j fail + +// check the result from M-mode +test9c: + li TEST_ID, 9 + li x5, PMPADDR10 + csrr x6, pmpaddr10 + beq x5, x6, pass + +fail: + li x2, 0xf00fff24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xf00fff20 + sw x0, 0(x2)
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/pmp/src/ld b/VexRiscv/src/test/cpp/raw/pmp/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} |