1 files changed, 36 insertions, 0 deletions
diff --git a/VexRiscv/src/test/scala/vexriscv/experimental/config.scala b/VexRiscv/src/test/scala/vexriscv/experimental/config.scala
new file mode 100644
index 0000000..d6eca55
--- /dev/null
+++ b/VexRiscv/src/test/scala/vexriscv/experimental/config.scala
@@ -0,0 +1,36 @@
+package vexriscv.experimental
+
+import spinal.core.SpinalVerilog
+import vexriscv.ip.InstructionCacheConfig
+import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
+import vexriscv.plugin._
+
+import scala.collection.mutable.ArrayBuffer
+
+object Presentation extends App{
+
+  val config = VexRiscvConfig()
+
+  config.plugins ++= List(
+//    new IBusSimplePlugin(resetVector = 0x80000000l),
+    new DBusSimplePlugin,
+    new CsrPlugin(CsrPluginConfig.smallest),
+    new DecoderSimplePlugin,
+    new RegFilePlugin(regFileReadyKind = plugin.SYNC),
+    new IntAluPlugin,
+    new SrcPlugin,
+    new MulDivIterativePlugin(
+      mulUnrollFactor = 4,
+      divUnrollFactor = 1
+    ),
+    new FullBarrelShifterPlugin,
+    new HazardSimplePlugin,
+    new BranchPlugin(
+      earlyBranch = false
+    ),
+    new YamlPlugin("cpu0.yaml")
+  )
+
+  new VexRiscv(config)
+}
+