diff options
Diffstat (limited to 'VexRiscv/src/test/scala/vexriscv/experimental')
4 files changed, 308 insertions, 0 deletions
diff --git a/VexRiscv/src/test/scala/vexriscv/experimental/Experiments.scala b/VexRiscv/src/test/scala/vexriscv/experimental/Experiments.scala new file mode 100644 index 0000000..1fead21 --- /dev/null +++ b/VexRiscv/src/test/scala/vexriscv/experimental/Experiments.scala @@ -0,0 +1,34 @@ +package vexriscv.experimental + +import spinal.core._ + +class Stageable[T <: Data](val dataType : T) extends HardType[T](dataType) with Nameable{ + setWeakName(this.getClass.getSimpleName.replace("$","")) +} + +trait Stage{ + def read[T <: Data](stageable : Stageable[T]) : T + def write[T <: Data](stageable : Stageable[T], value : T, cond : Bool = null) : Unit + + def haltBySelf : Bool //user settable, stuck the instruction, should only be set by the instruction itself + def haltByOthers : Bool //When settable, stuck the instruction, should only be set by something else than the stucked instruction + def removeIt : Bool //When settable, unschedule the instruction as if it was never executed (no side effect) + def flushAll : Bool //When settable, unschedule instructions in the current stage and all prior ones + + def isValid : Bool //Inform if a instruction is in the current stage + def isStuck : Bool //Inform if the instruction is stuck (haltItself || haltByOther) + def isStuckByOthers: Bool //Inform if the instruction is stuck by sombody else + def isRemoved : Bool //Inform if the instruction is going to be unschedule the current cycle + def isFlushed : Bool //Inform if the instruction is flushed (flushAll set in the current or subsequents stages) + def isFiring : Bool //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt) +} + +abstract class UnusedStage extends Stage +abstract class AsyncStage extends Stage +abstract class CycleStage extends Stage +abstract class SyncStage extends Stage +abstract class CutStage extends Stage + +abstract class PipelineStd{ + val prefetch, fetch, decode, execute, memory, writeback = 0 +}
\ No newline at end of file diff --git a/VexRiscv/src/test/scala/vexriscv/experimental/GenMicro.scala b/VexRiscv/src/test/scala/vexriscv/experimental/GenMicro.scala new file mode 100644 index 0000000..90666a7 --- /dev/null +++ b/VexRiscv/src/test/scala/vexriscv/experimental/GenMicro.scala @@ -0,0 +1,162 @@ +package vexriscv.experimental + +import spinal.core._ +import spinal.lib.eda.bench.{AlteraStdTargets, Bench, Rtl, XilinxStdTargets} +import spinal.lib.eda.icestorm.IcestormStdTargets +import vexriscv.demo.{GenSmallestNoCsr, Murax, MuraxConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} + +/** + * Created by spinalvm on 15.06.17. + */ +object GenMicro extends App{ + def cpu() = { + val removeOneFetchStage = true + val pessimisticHazard = true + val writeBackOpt = true + val rspHoldValue = true + val withCompliantCsr = true + val withCompliantCsrPlusEmulation = true + val earlyBranch = false + val noShifter = false + val onlyLoadWords = false + new VexRiscv( + config = VexRiscvConfig( + plugins = List( + // new PcManagerSimplePlugin( + // resetVector = 0x00000000l, + // relaxedPcCalculation = false + // ), + + new IBusSimplePlugin( + resetVector = 0x80000000l, + cmdForkOnSecondStage = false, + cmdForkPersistence = false, + prediction = NONE, + catchAccessFault = false, + compressedGen = false, + injectorStage = !removeOneFetchStage, + rspHoldValue = rspHoldValue + ), + new DBusSimplePlugin( + catchAddressMisaligned = withCompliantCsr, + catchAccessFault = false, + earlyInjection = writeBackOpt, + onlyLoadWords = onlyLoadWords + ), + new DecoderSimplePlugin( + catchIllegalInstruction = withCompliantCsrPlusEmulation + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = false, + readInExecute = removeOneFetchStage, + writeRfInMemoryStage = writeBackOpt + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = removeOneFetchStage + ), + if(!pessimisticHazard) + new HazardSimplePlugin( + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ) + else + new HazardPessimisticPlugin(), + new BranchPlugin( + earlyBranch = earlyBranch, + catchAddressMisaligned = withCompliantCsr, + fenceiGenAsAJump = withCompliantCsr + ), + new YamlPlugin("cpu0.yaml") + ) ++ (if(noShifter) Nil else List(new LightShifterPlugin)) + ++ (if(!withCompliantCsr) Nil else List(new CsrPlugin( + config = if(withCompliantCsrPlusEmulation)CsrPluginConfig( + catchIllegalAccess = true, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 0, + misaAccess = CsrAccess.NONE, + mtvecAccess = CsrAccess.NONE, + mtvecInit = 0x80000020l, + mepcAccess = CsrAccess.NONE, + mscratchGen = false, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.NONE, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = false, + ebreakGen = false, + wfiGenAsWait = false, + wfiGenAsNop = false, + ucycleAccess = CsrAccess.NONE, + noCsrAlu = true + ) else CsrPluginConfig( + catchIllegalAccess = false, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 0, + misaAccess = CsrAccess.READ_ONLY, + mtvecAccess = CsrAccess.WRITE_ONLY, + mtvecInit = 0x80000020l, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = true, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.READ_ONLY, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = true, + ebreakGen = true, + wfiGenAsWait = false, + wfiGenAsNop = true, + ucycleAccess = CsrAccess.NONE + ) + ))) + ) + ) + } + SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu()) +} + + + +object GenMicroSynthesis { + def main(args: Array[String]) { + val microNoCsr = new Rtl { + override def getName(): String = "MicroNoCsr" + override def getRtlPath(): String = "MicroNoCsr.v" + SpinalVerilog(GenMicro.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val smallestNoCsr = new Rtl { + override def getName(): String = "SmallestNoCsr" + override def getRtlPath(): String = "SmallestNoCsr.v" + SpinalVerilog(GenSmallestNoCsr.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val rtls = List(microNoCsr) +// val rtls = List(smallestNoCsr) + + val targets = IcestormStdTargets().take(1) ++ XilinxStdTargets( + vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" + ) ++ AlteraStdTargets( + quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/", + quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/" + ) + + + Bench(rtls, targets, "/eda/tmp/") + } +}
\ No newline at end of file diff --git a/VexRiscv/src/test/scala/vexriscv/experimental/PlicCost.scala b/VexRiscv/src/test/scala/vexriscv/experimental/PlicCost.scala new file mode 100644 index 0000000..79d5c66 --- /dev/null +++ b/VexRiscv/src/test/scala/vexriscv/experimental/PlicCost.scala @@ -0,0 +1,76 @@ +package vexriscv.experimental + +import spinal.core._ +import spinal.lib._ +import spinal.lib.bus.amba3.apb._ +import spinal.lib.eda.bench.{Bench, Rtl, XilinxStdTargets} +import spinal.lib.eda.icestorm.IcestormStdTargets +import spinal.lib.misc.plic._ +import vexriscv.VexRiscv +import vexriscv.demo.LinuxGen + +import scala.collection.mutable.ArrayBuffer + +class PlicBench(inputCount : Int) extends Component{ + val io = new Bundle { + val apb = slave(Apb3(addressWidth = 16, dataWidth = 32)) + val interrupts = in Bits(inputCount bits) + val cpuInterrupt = out Bool() + } + + + val priorityWidth = 1 + val gateways = ArrayBuffer[PlicGateway]() + + for(i <- 0 until inputCount) { + gateways += PlicGatewayActiveHigh( + source = io.interrupts(i), + id = 1 + i, + priorityWidth = priorityWidth + ) + } + + + val targets = Seq( + PlicTarget( + gateways = gateways, + priorityWidth = priorityWidth + ) + ) + io.cpuInterrupt := targets(0).iep + + val plicMapping = PlicMapping.light.copy( +// gatewayPriorityReadGen = true, +// gatewayPendingReadGen = true, +// targetThresholdReadGen = true + ) + + gateways.foreach(_.priority := 1) + targets.foreach(_.threshold := 0) + // targets.foreach(_.ie.foreach(_ := True)) + + val bus = Apb3SlaveFactory(io.apb) + val mapping = PlicMapper(bus, plicMapping)( + gateways = gateways, + targets = targets + ) +} + + +object PlicCost extends App{ + def rtlGen(inputCount : Int) = new Rtl { + override def getName(): String = s"PlicBench$inputCount" + override def getRtlPath(): String = s"PlicBench$inputCount.v" + SpinalVerilog(new PlicBench(inputCount).setDefinitionName(getRtlPath().split("\\.").head)) + } + + val rtls = List(8, 12, 16, 32).map(rtlGen) + // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) + // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) + // val rtls = List(fullNoMmu) + + val targets = IcestormStdTargets().take(1) + + + Bench(rtls, targets, "/eda/tmp") +} diff --git a/VexRiscv/src/test/scala/vexriscv/experimental/config.scala b/VexRiscv/src/test/scala/vexriscv/experimental/config.scala new file mode 100644 index 0000000..d6eca55 --- /dev/null +++ b/VexRiscv/src/test/scala/vexriscv/experimental/config.scala @@ -0,0 +1,36 @@ +package vexriscv.experimental + +import spinal.core.SpinalVerilog +import vexriscv.ip.InstructionCacheConfig +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} +import vexriscv.plugin._ + +import scala.collection.mutable.ArrayBuffer + +object Presentation extends App{ + + val config = VexRiscvConfig() + + config.plugins ++= List( +// new IBusSimplePlugin(resetVector = 0x80000000l), + new DBusSimplePlugin, + new CsrPlugin(CsrPluginConfig.smallest), + new DecoderSimplePlugin, + new RegFilePlugin(regFileReadyKind = plugin.SYNC), + new IntAluPlugin, + new SrcPlugin, + new MulDivIterativePlugin( + mulUnrollFactor = 4, + divUnrollFactor = 1 + ), + new FullBarrelShifterPlugin, + new HazardSimplePlugin, + new BranchPlugin( + earlyBranch = false + ), + new YamlPlugin("cpu0.yaml") + ) + + new VexRiscv(config) +} + |