add uart_rx_edge

3 files changed, 23 insertions, 0 deletions

diff --git a/sim/top_uart/makefile.sources b/sim/top_uart/makefile.sources
index c071757..37c4bda 100644
--- a/sim/top_uart/makefile.sources
+++ b/sim/top_uart/makefile.sources
@@ -6,6 +6,7 @@ SYN_SOURCE_FILES = \
 ../../src/uart_tx_shift.vhd \
 ../../src/top_uart.vhd \
 ../../src/uart_rx.vhd \
+../../src/uart_rx_edge.vhd \
 ../../src/uart_rx_shift.vhd \
 ../../src/uart_rx_baudcnt.vhd \
 ../../src/uart_rx_bitcnt.vhd
diff --git a/src/uart_rx_edge.vhd b/src/uart_rx_edge.vhd
new file mode 100644
index 0000000..9a85f92
--- /dev/null
+++ b/src/uart_rx_edge.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uart_rx_edge is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    rxd_i   : in std_ulogic;
+    rxd_o   : out std_ulogic;
+    edge_o  : out std_ulogic);
+end entity;
+
+architecture rtl of uart_rx_edge is
+  signal sr, nsr : std_ulogic_vector(1 downto 0);
+begin
+  sr <= "00" when rst_n = '0' else nsr when rising_edge(clk);
+  nsr <= rxd_i & sr(1);
+  rxd_o <= sr(0);
+  edge_o <= '1' when sr = "01" else '0';
+end architecture rtl;
+
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index 01449fe..71576ef 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -30,6 +30,7 @@ top_uart.files = [
     ,'src/baudcnt.vhd'
     ,'src/uart_tx_shift.vhd'
     ,'src/uart_rx_shift.vhd'
+    ,'src/uart_rx_edge.vhd'    
     ,'src/uart_rx_baudcnt.vhd'
     ,'src/uart_rx_bitcnt.vhd'
     ,'src/uart_rx.vhd'