uart rx

7 files changed, 107 insertions, 5 deletions

diff --git a/sim/top_uart/makefile.sources b/sim/top_uart/makefile.sources
index c5493f3..c071757 100644
--- a/sim/top_uart/makefile.sources
+++ b/sim/top_uart/makefile.sources
@@ -4,4 +4,8 @@ SYN_SOURCE_FILES = \
 ../../src/baudcnt.vhd \
 ../../src/edge.vhd \
 ../../src/uart_tx_shift.vhd \
-../../src/top_uart.vhd
+../../src/top_uart.vhd \
+../../src/uart_rx.vhd \
+../../src/uart_rx_shift.vhd \
+../../src/uart_rx_baudcnt.vhd \
+../../src/uart_rx_bitcnt.vhd
diff --git a/src/t_top_uart.vhd b/src/t_top_uart.vhd
index ddec0cb..b3a0d95 100644
--- a/src/t_top_uart.vhd
+++ b/src/t_top_uart.vhd
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity t_top_uart is
 end entity;
@@ -18,6 +19,11 @@ architecture beh of t_top_uart is
   signal sim_ledg    : std_ulogic_vector(3 downto 0);
   signal sim_exp     : std_ulogic_vector(7 downto 0);
 
+  -- UART Transmitter Simulation
+  constant bittime   : time := 17361 ns; -- 57600 Baud
+  constant txstring  : string := "Hallo ihr da!";
+  signal txchar      : std_ulogic_vector(7 downto 0);
+
   signal simstop : boolean := false;
 
 begin
@@ -37,8 +43,25 @@ begin
   -- Stimuli reset generator
   sim_rst_n <= '0', '1' after 55 ns;
 
-  -- UART input - not used...
-  sim_uart_rxd <= '0';
+  -- UART Transmitter Simulation
+  uart_tx_p : process
+  begin
+    sim_uart_rxd <= '1'; -- idle
+    wait for 300 ns;
+    for i in 1 to txstring'length loop
+      sim_uart_rxd <= '0'; -- start bit
+      txchar <= std_ulogic_vector(to_unsigned(character'pos(txstring(i)),8));
+      wait for bittime;
+      for bitidx in 0 to 7 loop
+        sim_uart_rxd <= txchar(bitidx);
+        wait for bittime;
+      end loop;
+      sim_uart_rxd <= '1';
+      wait for 2 * bittime; -- 2 Stopbits
+    end loop;
+    simstop <= true;
+    wait;
+    end process;
 
   -- Stimuli key push
   stim_p : process
@@ -50,7 +73,7 @@ begin
     wait for 100 ns;
     sim_x <= '0';
     wait for 600 ns;
-    simstop <= true;
+    --simstop <= true;
     wait;
   end process ;
 
diff --git a/src/uart_rx.vhd b/src/uart_rx.vhd
new file mode 100644
index 0000000..616b181
--- /dev/null
+++ b/src/uart_rx.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uart_rx is
+  port (
+    clk        : in std_ulogic;
+    rst_n      : in std_ulogic;
+    uart_rxd_i : in std_ulogic;
+    rxd_o      : out std_ulogic_vector(7 downto 0);
+    dv_o       : out std_ulogic);
+end entity;
+
+architecture rtl of uart_rx is
+begin
+
+end architecture rtl;
+
diff --git a/src/uart_rx_baudcnt.vhd b/src/uart_rx_baudcnt.vhd
new file mode 100644
index 0000000..16a24a9
--- /dev/null
+++ b/src/uart_rx_baudcnt.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_rx_baudcnt is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    sres_i  : in std_ulogic;
+    en_h_o  : out std_ulogic;
+    en_f_o  : out std_ulogic);
+end entity;
+
+architecture rtl of uart_rx_baudcnt is
+begin
+
+end architecture rtl;
diff --git a/src/uart_rx_bitcnt.vhd b/src/uart_rx_bitcnt.vhd
new file mode 100644
index 0000000..7aec27a
--- /dev/null
+++ b/src/uart_rx_bitcnt.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_rx_bitcnt is
+  port (
+    clk        : in std_ulogic;
+    rst_n      : in std_ulogic;
+    edge_i     : in std_ulogic;
+    en_h_i     : in std_ulogic;
+    en_f_i     : in std_ulogic;
+    rx_baudcnt_res_o : out std_ulogic;
+    rx_shift_o : out std_ulogic;
+    dv_o       : out std_ulogic);
+end entity;
+
+architecture rtl of uart_rx_bitcnt is
+begin
+end architecture rtl;
+
diff --git a/src/uart_rx_shift.vhd b/src/uart_rx_shift.vhd
new file mode 100644
index 0000000..273931c
--- /dev/null
+++ b/src/uart_rx_shift.vhd
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uart_rx_shift is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    shift_i : in std_ulogic;
+    ser_i   : in std_ulogic;
+    d_o     : out std_ulogic_vector(7 downto 0));
+end entity;
+
+architecture rtl of uart_rx_shift is
+begin
+end architecture rtl;
+
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index 2460aad..01449fe 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -29,6 +29,11 @@ top_uart.files = [
     'src/edge.vhd'
     ,'src/baudcnt.vhd'
     ,'src/uart_tx_shift.vhd'
+    ,'src/uart_rx_shift.vhd'
+    ,'src/uart_rx_baudcnt.vhd'
+    ,'src/uart_rx_bitcnt.vhd'
+    ,'src/uart_rx.vhd'
     ,'src/top_uart.vhd'
     ,'src/t_top_uart.vhd'
-    ]
\ No newline at end of file
+    ]
+