top_hex: add adder

2 files changed, 25 insertions, 3 deletions

diff --git a/pnr/top_hex/top_hex_pins.tcl b/pnr/top_hex/top_hex_pins.tcl
index 5dd0a78..a78c0e2 100644
--- a/pnr/top_hex/top_hex_pins.tcl
+++ b/pnr/top_hex/top_hex_pins.tcl
@@ -41,3 +41,10 @@ set_location_assignment PIN_C1 -to HEX2[3]
 set_location_assignment PIN_E3 -to HEX2[4]
 set_location_assignment PIN_E4 -to HEX2[5]
 set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
diff --git a/src/top_hex.vhd b/src/top_hex.vhd
index cfe2d33..af0da77 100644
--- a/src/top_hex.vhd
+++ b/src/top_hex.vhd
@@ -1,26 +1,41 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity top_hex is 
 port ( SW   : in      std_ulogic_vector(9 downto 0);
        HEX0 : out     std_ulogic_vector(6 downto 0);
        HEX1 : out     std_ulogic_vector(6 downto 0);
        HEX2 : out     std_ulogic_vector(6 downto 0);
+       HEX3 : out     std_ulogic_vector(6 downto 0);
        LEDR : out     std_ulogic_vector(9 downto 0));
 end entity;
 
 architecture rtl of top_hex is
+  signal sa : signed(4 downto 0);
+  signal sb : signed(4 downto 0);
+  signal sum : signed(4 downto 0);
 begin
 
 LEDR <= SW;
 
+sa <= signed(SW(4 downto 0));
+sb <= signed(SW(9 downto 5));
+sum <= sa + sb;
+
+bin2seg_i1: entity work.bin2seg
+ port map(
+    bin_i => "000" & std_ulogic(sum(4)),
+    seg_o => HEX1
+);
+
 bin2seg_i0: entity work.bin2seg
  port map(
-    bin_i => SW(3 downto 0),
+    bin_i => std_ulogic_vector(sum(3 downto 0)),
     seg_o => HEX0
 );
 
-HEX1 <= "1111111";
-HEX2 <= "1111111";
+HEX2 <= "1111111" when sa > -1 else "0000000";
+HEX3 <= "1111111";
 
 end architecture rtl;