top_shift: add edge.vhd and ringcnt.vhd as empty modules

4 files changed, 48 insertions, 14 deletions

diff --git a/src/edge.vhd b/src/edge.vhd
new file mode 100644
index 0000000..23dba70
--- /dev/null
+++ b/src/edge.vhd
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity edge is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    x_i     : in std_ulogic;
+    edge_o  : out std_ulogic);
+end entity;
+
+architecture rtl of edge is
+begin
+
+end architecture rtl;
+
diff --git a/src/ringcnt.vhd b/src/ringcnt.vhd
new file mode 100644
index 0000000..5fc0d60
--- /dev/null
+++ b/src/ringcnt.vhd
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ringcnt is 
+end entity;
+
+architecture rtl of ringcnt is
+begin
+
+end architecture rtl; 
+
diff --git a/src/t_top_shift.vhd b/src/t_top_shift.vhd
index 996b6d1..ddf76a1 100644
--- a/src/t_top_shift.vhd
+++ b/src/t_top_shift.vhd
@@ -37,10 +37,21 @@ begin
   sim_rst_n <= '0', '1' after 55 ns;
 
   -- Stimuli key push
-  sim_x <= '0', '1' after 135 ns, '0' after 195 ns;
-
-  -- Simulation stopper
-  simstop <= true after 300 ns;
+  stim_p : process
+  begin
+    sim_x <= '0';
+    wait until rising_edge(sim_rst_n);
+    for i in 0 to 5 loop
+      wait until falling_edge(sim_clk);
+    end loop;
+    sim_x <= '1';
+    wait until falling_edge(sim_clk);
+    wait until falling_edge(sim_clk);
+    sim_x <= '0';
+    wait for 200 ns;
+    simstop <= true;
+    wait;
+  end process ;
 
   -- Device under test instantiation
   dut : entity work.top_shift
@@ -57,7 +68,7 @@ begin
   sim_key(0) <= sim_rst_n;
   sim_key(1) <= sim_x;
   sim_key(3 downto 2) <= "00";
-  sim_sw <= "1010000101";
+  sim_sw <= "1010000001";
 
   -- Check the expansion port y output
   sim_y <= sim_exp(3);
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
index f6036bc..d0c6f44 100644
--- a/src/top_shift.vhd
+++ b/src/top_shift.vhd
@@ -14,8 +14,8 @@ architecture rtl of top_shift is
   signal clk     : std_ulogic;
   signal rst_n   : std_ulogic;
   signal x       : std_ulogic;
-  signal sr, srnext : std_ulogic_vector(0 to 1);
-  signal en       : std_ulogic;
+  signal sr, srnext : std_ulogic_vector(1 downto 0);
+  signal en      : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
@@ -33,15 +33,11 @@ begin
   sr <= "00" when rst_n = '0' else srnext when rising_edge(clk);
 
   -- Implement the shift register function with next state logic
-  srnext(0) <= x;
-  srnext(1) <= sr(0);
+  srnext(1) <= x;
+  srnext(0) <= sr(1);
 
   -- Compute the output function from the shift register content
-  en <= sr(0) xor sr(1);
-
-  --------------------------
-  -- New code here
-  --------------------------
+  en <= sr(1) xor sr(0);
 
   -- Set the outputs;
   EXP <= (7 downto 4 => '0',