add top_shift and simulation

2 files changed, 120 insertions, 0 deletions

diff --git a/src/t_top_shift.vhd b/src/t_top_shift.vhd
new file mode 100644
index 0000000..996b6d1
--- /dev/null
+++ b/src/t_top_shift.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_top_shift is
+end entity;
+
+architecture beh of t_top_shift is
+
+  signal sim_clk     : std_ulogic;
+  signal sim_rst_n   : std_ulogic;
+  signal sim_x       : std_ulogic;
+  signal sim_y       : std_ulogic;
+
+  signal sim_sw      : std_ulogic_vector(9 downto 0);
+  signal sim_key     : std_ulogic_vector(3 downto 0);
+  signal sim_ledr    : std_ulogic_vector(9 downto 0);
+  signal sim_ledg    : std_ulogic_vector(3 downto 0);
+  signal sim_exp     : std_ulogic_vector(7 downto 0);
+
+  signal simstop : boolean := false;
+
+begin
+
+  -- Stimuli clock generator
+  clk_p : process
+  begin
+    sim_clk <= '0';
+    wait for 10 ns;
+    sim_clk <= '1';
+    wait for 10 ns;
+    if simstop then
+      wait;
+    end if;
+  end process;
+
+  -- Stimuli reset generator
+  sim_rst_n <= '0', '1' after 55 ns;
+
+  -- Stimuli key push
+  sim_x <= '0', '1' after 135 ns, '0' after 195 ns;
+
+  -- Simulation stopper
+  simstop <= true after 300 ns;
+
+  -- Device under test instantiation
+  dut : entity work.top_shift
+   port map(
+      SW   => sim_sw,
+      KEY  => sim_key,
+      CLOCK_50 => sim_clk,
+      EXP  => sim_exp,
+      LEDG => sim_ledg,
+      LEDR => sim_ledr
+  );
+
+  -- Connect stimuli to input signals
+  sim_key(0) <= sim_rst_n;
+  sim_key(1) <= sim_x;
+  sim_key(3 downto 2) <= "00";
+  sim_sw <= "1010000101";
+
+  -- Check the expansion port y output
+  sim_y <= sim_exp(3);
+ 
+end architecture beh;
\ No newline at end of file
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
new file mode 100644
index 0000000..f6036bc
--- /dev/null
+++ b/src/top_shift.vhd
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top_shift is 
+port ( SW       : in  std_ulogic_vector(9 downto 0);
+       KEY      : in  std_ulogic_vector(3 downto 0);
+       CLOCK_50 : in  std_ulogic;
+       EXP      : out std_ulogic_vector(7 downto 0);
+       LEDG     : out std_ulogic_vector(3 downto 0);
+       LEDR     : out std_ulogic_vector(9 downto 0));
+end entity;
+
+architecture rtl of top_shift is
+  signal clk     : std_ulogic;
+  signal rst_n   : std_ulogic;
+  signal x       : std_ulogic;
+  signal sr, srnext : std_ulogic_vector(0 to 1);
+  signal en       : std_ulogic;
+begin
+  -- Assign the inputs to signals with reasonable names
+  clk <= CLOCK_50;
+  rst_n <= KEY(0);
+  x <= KEY(1);
+
+  -------------------------
+  -- The edge detector
+  -------------------------
+  -- Designpattern Register
+  -- Create a register with two flipflops with low active
+  -- asynchronous reset.
+  -- D-Input is connected to srnext
+  -- Q Outputs are connected to sr
+  sr <= "00" when rst_n = '0' else srnext when rising_edge(clk);
+
+  -- Implement the shift register function with next state logic
+  srnext(0) <= x;
+  srnext(1) <= sr(0);
+
+  -- Compute the output function from the shift register content
+  en <= sr(0) xor sr(1);
+
+  --------------------------
+  -- New code here
+  --------------------------
+
+  -- Set the outputs;
+  EXP <= (7 downto 4 => '0',
+          3 => en,
+          2 => x,
+          1 => rst_n,
+          0 => clk);
+  LEDR <= SW;
+  LEDG <= KEY;
+
+end architecture rtl;
\ No newline at end of file