1 files changed, 26 insertions, 3 deletions
diff --git a/src/t_top_uart.vhd b/src/t_top_uart.vhd
index ddec0cb..b3a0d95 100644
--- a/src/t_top_uart.vhd
+++ b/src/t_top_uart.vhd
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity t_top_uart is
 end entity;
@@ -18,6 +19,11 @@ architecture beh of t_top_uart is
   signal sim_ledg    : std_ulogic_vector(3 downto 0);
   signal sim_exp     : std_ulogic_vector(7 downto 0);
 
+  -- UART Transmitter Simulation
+  constant bittime   : time := 17361 ns; -- 57600 Baud
+  constant txstring  : string := "Hallo ihr da!";
+  signal txchar      : std_ulogic_vector(7 downto 0);
+
   signal simstop : boolean := false;
 
 begin
@@ -37,8 +43,25 @@ begin
   -- Stimuli reset generator
   sim_rst_n <= '0', '1' after 55 ns;
 
-  -- UART input - not used...
-  sim_uart_rxd <= '0';
+  -- UART Transmitter Simulation
+  uart_tx_p : process
+  begin
+    sim_uart_rxd <= '1'; -- idle
+    wait for 300 ns;
+    for i in 1 to txstring'length loop
+      sim_uart_rxd <= '0'; -- start bit
+      txchar <= std_ulogic_vector(to_unsigned(character'pos(txstring(i)),8));
+      wait for bittime;
+      for bitidx in 0 to 7 loop
+        sim_uart_rxd <= txchar(bitidx);
+        wait for bittime;
+      end loop;
+      sim_uart_rxd <= '1';
+      wait for 2 * bittime; -- 2 Stopbits
+    end loop;
+    simstop <= true;
+    wait;
+    end process;
 
   -- Stimuli key push
   stim_p : process
@@ -50,7 +73,7 @@ begin
     wait for 100 ns;
     sim_x <= '0';
     wait for 600 ns;
-    simstop <= true;
+    --simstop <= true;
     wait;
   end process ;