uart rx solutionsolutions

6 files changed, 102 insertions, 11 deletions

diff --git a/sim/top_uart/view_signals.gtkw b/sim/top_uart/view_signals.gtkw
index 4dc4a96..2b8c8f0 100644
--- a/sim/top_uart/view_signals.gtkw
+++ b/sim/top_uart/view_signals.gtkw
@@ -1,20 +1,24 @@
 [*]
 [*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
-[*] Tue May 14 14:43:08 2024
+[*] Mon May 27 19:50:24 2024
 [*]
 [dumpfile] "/home/caeuser/projects/dtlab/sim/top_uart/t_top_uart.ghw"
-[dumpfile_mtime] "Tue May 14 14:41:32 2024"
-[dumpfile_size] 2702
+[dumpfile_mtime] "Mon May 27 19:39:07 2024"
+[dumpfile_size] 4592393
 [savefile] "/home/caeuser/projects/dtlab/sim/top_uart/view_signals.gtkw"
 [timestart] 0
 [size] 1170 600
-[pos] -1 -1
-*-28.012674 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[pos] 60 -60
+*-36.538273 171050000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.t_top_uart.
 [treeopen] top.t_top_uart.top_uart_inst.
 [treeopen] top.t_top_uart.top_uart_inst.baudcnt_inst.
-[sst_width] 245
+[treeopen] top.t_top_uart.top_uart_inst.uart_rx_inst.
+[treeopen] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.
+[treeopen] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_bitcnt_inst.
+[treeopen] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.
+[sst_width] 332
 [signals_width] 169
 [sst_expanded] 1
 [sst_vpaned_height] 259
@@ -27,7 +31,23 @@ top.t_top_uart.sim_rst_n
 top.t_top_uart.sim_x
 top.t_top_uart.top_uart_inst.start
 top.t_top_uart.top_uart_inst.en
-@25
+@24
 #{top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[9:0]} top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[9] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[8] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[7] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[6] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[5] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[4] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[3] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[2] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[1] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[0]
+@28
+top.t_top_uart.sim_uart_txd
+@820
+#{top.t_top_uart.txchar[7:0]} top.t_top_uart.txchar[7] top.t_top_uart.txchar[6] top.t_top_uart.txchar[5] top.t_top_uart.txchar[4] top.t_top_uart.txchar[3] top.t_top_uart.txchar[2] top.t_top_uart.txchar[1] top.t_top_uart.txchar[0]
+@29
+top.t_top_uart.sim_uart_rxd
+@28
+top.t_top_uart.top_uart_inst.uart_rx_inst.edge
+top.t_top_uart.top_uart_inst.uart_rx_inst.shift
+@22
+#{top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_bitcnt_inst.cnt[3:0]} top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_bitcnt_inst.cnt[3] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_bitcnt_inst.cnt[2] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_bitcnt_inst.cnt[1] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_bitcnt_inst.cnt[0]
+#{top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[9:0]} top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[9] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[8] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[7] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[6] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[5] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[4] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[3] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[2] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[1] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_baudcnt_inst.cnt[0]
+@820
+#{top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[7:0]} top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[7] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[6] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[5] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[4] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[3] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[2] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[1] top.t_top_uart.top_uart_inst.uart_rx_inst.uart_rx_shift_inst.sr[0]
+@28
+top.t_top_uart.top_uart_inst.dv
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/src/top_uart.vhd b/src/top_uart.vhd
index d53f06d..abe1e96 100644
--- a/src/top_uart.vhd
+++ b/src/top_uart.vhd
@@ -17,6 +17,7 @@ architecture rtl of top_uart is
   signal rst_n   : std_ulogic;
   signal en, txd : std_ulogic;
   signal start   : std_ulogic;
+  signal dv : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
@@ -48,14 +49,26 @@ begin
       tx_o    => txd
   );
 
+  uart_rx_inst: entity work.uart_rx
+   port map(
+      clk         => clk,
+      rst_n       => rst_n,
+      uart_rxd_i  => UART_RXD,
+      rxd_o       => LEDR(7 downto 0),
+      dv_o        => dv
+  );
+
   -- Set the outputs;
-  EXP(7 downto 4) <= "0000";
-  EXP(3 downto 0) <= (3 => txd,
+  EXP(7 downto 6) <= "00";
+  EXP(5 downto 0) <= (
+          5 => dv,
+          4 => UART_RXD,
+          3 => txd,
           2 => en,
           1 => rst_n,
           0 => clk);
   UART_TXD <= txd;
-  LEDR <= SW;
+  LEDR(9 downto 8) <= "00";
   LEDG <= KEY;
 
 end architecture rtl;
\ No newline at end of file
diff --git a/src/uart_rx.vhd b/src/uart_rx.vhd
index 616b181..37d8486 100644
--- a/src/uart_rx.vhd
+++ b/src/uart_rx.vhd
@@ -11,7 +11,48 @@ entity uart_rx is
 end entity;
 
 architecture rtl of uart_rx is
+  signal edge, shift, baud_en_f, baud_en_h, baud_res : std_ulogic;
+  signal uart_rxd_sync : std_ulogic;
 begin
 
+uart_rx_edge_inst: entity work.uart_rx_edge
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    rxd_i => uart_rxd_i,
+    rxd_o => uart_rxd_sync,
+    edge_o => edge
+);
+
+uart_rx_shift_inst: entity work.uart_rx_shift
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    shift_i => shift,
+    ser_i => uart_rxd_sync,
+    d_o => rxd_o
+);
+
+uart_rx_baudcnt_inst: entity work.uart_rx_baudcnt
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    sres_i => baud_res,
+    en_h_o => baud_en_h,
+    en_f_o => baud_en_f
+);
+
+uart_rx_bitcnt_inst: entity work.uart_rx_bitcnt
+ port map(
+    clk => clk,
+    rst_n => rst_n,
+    edge_i => edge,
+    en_h_i => baud_en_h,
+    en_f_i => baud_en_f,
+    rx_baudcnt_res_o => baud_res,
+    rx_shift_o => shift,
+    dv_o => dv_o
+);
+
 end architecture rtl;
 
diff --git a/src/uart_rx_baudcnt.vhd b/src/uart_rx_baudcnt.vhd
index 16a24a9..779567b 100644
--- a/src/uart_rx_baudcnt.vhd
+++ b/src/uart_rx_baudcnt.vhd
@@ -12,6 +12,10 @@ entity uart_rx_baudcnt is
 end entity;
 
 architecture rtl of uart_rx_baudcnt is
+  signal cnt, ncnt : unsigned(9 downto 0);
 begin
-
+  cnt <= "0000000000" when rst_n = '0' else ncnt when rising_edge(clk);
+  ncnt <= "0000000000" when cnt = 867 or sres_i = '1' else cnt + 1;
+  en_f_o <= '1' when cnt = 867 else '0';
+  en_h_o <= '1' when cnt = 867/2 else '0';
 end architecture rtl;
diff --git a/src/uart_rx_bitcnt.vhd b/src/uart_rx_bitcnt.vhd
index 7aec27a..78e8a1c 100644
--- a/src/uart_rx_bitcnt.vhd
+++ b/src/uart_rx_bitcnt.vhd
@@ -15,6 +15,15 @@ entity uart_rx_bitcnt is
 end entity;
 
 architecture rtl of uart_rx_bitcnt is
+  signal cnt, ncnt : unsigned(3 downto 0);
 begin
+  cnt <= "0000" when rst_n = '0' else ncnt when rising_edge(clk);
+  ncnt <= "0001" when edge_i = '1' and cnt = 0 else
+    cnt + 1 when en_f_i = '1' and cnt > 0 and cnt < 10 else
+    "0000" when en_h_i = '1' and cnt = 10 else cnt;
+
+  rx_shift_o <= '1' when cnt >= 2 and cnt <= 9 and en_h_i = '1' else '0';
+  dv_o <= '1' when cnt = 9 and en_f_i = '1' else '0';
+  rx_baudcnt_res_o <= '1' when cnt = 0 else '0';
 end architecture rtl;
 
diff --git a/src/uart_rx_shift.vhd b/src/uart_rx_shift.vhd
index 273931c..30a8403 100644
--- a/src/uart_rx_shift.vhd
+++ b/src/uart_rx_shift.vhd
@@ -11,6 +11,10 @@ entity uart_rx_shift is
 end entity;
 
 architecture rtl of uart_rx_shift is
+  signal sr, nsr : std_ulogic_vector(7 downto 0);
 begin
+  sr <= "00000000" when rst_n = '0' else nsr when rising_edge(clk);
+  nsr <= ser_i & sr(7 downto 1) when shift_i = '1' else sr;
+  d_o <= sr;
 end architecture rtl;