added de1_adc

4 files changed, 130 insertions, 50 deletions

diff --git a/pnr/de1_adc/de1_adc_pins.tcl b/pnr/de1_adc/de1_adc_pins.tcl
new file mode 100644
index 0000000..5921f2b
--- /dev/null
+++ b/pnr/de1_adc/de1_adc_pins.tcl
@@ -0,0 +1,94 @@
+# Pin Configuration 
+
+set_location_assignment PIN_L1  -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY0
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+# DAC Pins on GPIO Header
+set_location_assignment  PIN_C19  -to DAC_CLK_A
+set_location_assignment  PIN_D19  -to DAC_CLK_B
+set_location_assignment  PIN_C18  -to DAC_DA[0]
+set_location_assignment  PIN_F15  -to DAC_DA[10]
+set_location_assignment  PIN_E14  -to DAC_DA[11]
+set_location_assignment  PIN_G15  -to DAC_DA[12]
+set_location_assignment  PIN_H13  -to DAC_DA[13]
+set_location_assignment  PIN_D16  -to DAC_DA[1]
+set_location_assignment  PIN_C17  -to DAC_DA[2]
+set_location_assignment  PIN_D15  -to DAC_DA[3]
+set_location_assignment  PIN_D14  -to DAC_DA[4]
+set_location_assignment  PIN_F13  -to DAC_DA[5]
+set_location_assignment  PIN_C14  -to DAC_DA[6]
+set_location_assignment  PIN_F12  -to DAC_DA[7]
+set_location_assignment  PIN_G16  -to DAC_DA[8]
+set_location_assignment  PIN_E15  -to DAC_DA[9]
+set_location_assignment  PIN_P15  -to DAC_DB[0]
+set_location_assignment  PIN_G20  -to DAC_DB[10]
+set_location_assignment  PIN_E19  -to DAC_DB[11]
+set_location_assignment  PIN_F20  -to DAC_DB[12]
+set_location_assignment  PIN_D20  -to DAC_DB[13]
+set_location_assignment  PIN_N22  -to DAC_DB[1]
+set_location_assignment  PIN_N15  -to DAC_DB[2]
+set_location_assignment  PIN_N21  -to DAC_DB[3]
+set_location_assignment  PIN_J15  -to DAC_DB[4]
+set_location_assignment  PIN_G17  -to DAC_DB[5]
+set_location_assignment  PIN_H18  -to DAC_DB[6]
+set_location_assignment  PIN_H17  -to DAC_DB[7]
+set_location_assignment  PIN_G18  -to DAC_DB[8]
+set_location_assignment  PIN_E18  -to DAC_DB[9]
+set_location_assignment  PIN_P18  -to DAC_MODE
+set_location_assignment  PIN_C20  -to DAC_WRT_A
+set_location_assignment  PIN_P17  -to DAC_WRT_B
+set_location_assignment  PIN_C21  -to ADC_CLK_A
+set_location_assignment  PIN_D21  -to ADC_CLK_B
+set_location_assignment  PIN_L18  -to ADC_OEB_A
+set_location_assignment  PIN_K20  -to ADC_OEB_B
+set_location_assignment  PIN_J18  -to POWER_ON
+# ADC Pins on GPIO
+set_location_assignment  PIN_C22  -to ADC_DA[0]
+set_location_assignment  PIN_K21  -to ADC_DA[10]
+set_location_assignment  PIN_J19  -to ADC_DA[11]
+set_location_assignment  PIN_K22  -to ADC_DA[12]
+set_location_assignment  PIN_J20  -to ADC_DA[13]
+set_location_assignment  PIN_D22  -to ADC_DA[1]
+set_location_assignment  PIN_E21  -to ADC_DA[2]
+set_location_assignment  PIN_F21  -to ADC_DA[3]
+set_location_assignment  PIN_E22  -to ADC_DA[4]
+set_location_assignment  PIN_F22  -to ADC_DA[5]
+set_location_assignment  PIN_G21  -to ADC_DA[6]
+set_location_assignment  PIN_J21  -to ADC_DA[7]
+set_location_assignment  PIN_G22  -to ADC_DA[8]
+set_location_assignment  PIN_J22  -to ADC_DA[9]
+set_location_assignment  PIN_B13   -to ADC_DB[0]
+set_location_assignment  PIN_A19  -to ADC_DB[10]
+set_location_assignment  PIN_A20  -to ADC_DB[11]
+set_location_assignment  PIN_B19  -to ADC_DB[12]
+set_location_assignment  PIN_B20  -to ADC_DB[13]
+set_location_assignment  PIN_B14   -to ADC_DB[1]
+set_location_assignment  PIN_A15  -to ADC_DB[2]
+set_location_assignment  PIN_A16  -to ADC_DB[3]
+set_location_assignment  PIN_B15  -to ADC_DB[4]
+set_location_assignment  PIN_B16  -to ADC_DB[5]
+set_location_assignment  PIN_A17  -to ADC_DB[6]
+set_location_assignment  PIN_A18  -to ADC_DB[7]
+set_location_assignment  PIN_B17  -to ADC_DB[8]
+set_location_assignment  PIN_B18  -to ADC_DB[9]
+set_location_assignment  PIN_A13  -to ADC_OTR_A
+set_location_assignment  PIN_A14  -to ADC_OTR_B
diff --git a/pnr/de1_adc/de1_adc_special.sdc b/pnr/de1_adc/de1_adc_special.sdc
new file mode 100644
index 0000000..17260a6
--- /dev/null
+++ b/pnr/de1_adc/de1_adc_special.sdc
@@ -0,0 +1,21 @@
+create_clock -period 20.000 -name CLOCK_50 [get_ports CLOCK_50]
+
+set default_inputs [get_ports KEY0]
+set default_inputs [add_to_collection $default_inputs [get_ports ADC_OTR*]]
+
+# Some clock for ADC/DAC Board
+set clock_outputs [get_ports ADC_CLK*]
+set clock_outputs [add_to_collection $clock_outputs [get_ports DAC_CLK*]]
+set clock_outputs [add_to_collection $clock_outputs [get_ports DAC_WRT*]]
+
+set default_outputs [remove_from_collection [all_outputs] [get_ports DAC_D*]] 
+set default_outputs [remove_from_collection $default_outputs $clock_outputs]
+
+# Default Timing Constrains for Inputs/Outputs
+set_input_delay -clock CLOCK_50 5 $default_inputs
+set_output_delay -clock CLOCK_50  5 $default_outputs
+# Special Timing for ADC and DAC Data I/O
+set_input_delay -clock CLOCK_50 17 [get_ports ADC_D*]
+set_output_delay -clock CLOCK_50 -clock_fall 7 [get_ports DAC_D*]
+# Special Timing for clock outputs 
+set_output_delay -clock CLOCK_50 2 $clock_outputs
diff --git a/pnr/de1_adc/makefile b/pnr/de1_adc/makefile
new file mode 100644
index 0000000..cd0e30e
--- /dev/null
+++ b/pnr/de1_adc/makefile
@@ -0,0 +1,14 @@
+SIM_PROJECT_NAME = de1_adc
+PROJECT = $(SIM_PROJECT_NAME)
+
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+SOURCE_FILES = ../../src/de1_adc_rtl.vhd 
+
+include ../makefile
+
+# Use the specific sdc file
+$(PROJECT).sdc: $(PROJECT)_special.sdc
+	ln -s $(PROJECT)_special.sdc $(PROJECT).sdc
diff --git a/src/de1_adc_rtl.vhd b/src/de1_adc_rtl.vhd
index d82c892..ec18462 100644
--- a/src/de1_adc_rtl.vhd
+++ b/src/de1_adc_rtl.vhd
@@ -2,10 +2,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
--- PLL for 100 MHz speed
-library altera_mf;
-use altera_mf.all;
-
 entity de1_adc is 
   port ( CLOCK_50 : in  std_ulogic;         
          SW       : in  std_ulogic_vector(9 downto 0); 
@@ -31,57 +27,12 @@ end entity;
 
 architecture rtl of de1_adc is
 
-    -- Altera PLL
-  component altpll
-    generic (
-      clk0_divide_by         : natural;
-      clk0_duty_cycle        : natural;
-      clk0_multiply_by       : natural;
---              clk0_phase_shift                : STRING;
---              compensate_clock                : STRING;
-      inclk0_input_frequency : natural;
---              intended_device_family          : STRING;
---              lpm_hint                : STRING;
---              lpm_type                : STRING;
-      operation_mode         : string;
-      port_inclk0            : string;
-      port_clk0              : string
-      );
-    port (
-      clk   : out std_logic_vector (5 downto 0);
-      inclk : in  std_logic_vector (1 downto 0)
-      );
-  end component;
-
-  signal pll_inclk : std_logic_vector(1 downto 0);
-  signal pll_outclk : std_logic_vector(5 downto 0);
-
   signal clk,rst_n : std_ulogic;
   signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0);
   
 begin
 
-    pll_i0 : altpll
-    generic map (
-      clk0_divide_by         => 10,
-      clk0_duty_cycle        => 50,
-      clk0_multiply_by       => 13,
---              clk0_phase_shift => "0",
---              compensate_clock => "CLK0",
-      inclk0_input_frequency => 20000,
-      operation_mode         => "NORMAL",
-      port_inclk0            => "PORT_USED",
-      port_clk0              => "PORT_USED"
-      )
-    port map (
-      inclk => pll_inclk,
-      clk   => pll_outclk
-      );
-
-  pll_inclk(0) <= CLOCK_50;
-  pll_inclk(1) <= '0';
-  clk <= pll_outclk(0);
-  --clk <= CLOCK_50;
+  clk <= CLOCK_50;
 
   rst_n <= KEY0;
   LEDR <= "00000000" & ADC_OTR_A & ADC_OTR_B when rising_edge(clk);