diff options
| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /pnr/de1_audio | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'pnr/de1_audio')
| -rw-r--r-- | pnr/de1_audio/de1_audio_pins.tcl | 23 | ||||
| -rw-r--r-- | pnr/de1_audio/makefile | 16 |
2 files changed, 39 insertions, 0 deletions
diff --git a/pnr/de1_audio/de1_audio_pins.tcl b/pnr/de1_audio/de1_audio_pins.tcl new file mode 100644 index 0000000..28fe709 --- /dev/null +++ b/pnr/de1_audio/de1_audio_pins.tcl @@ -0,0 +1,23 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] + + diff --git a/pnr/de1_audio/makefile b/pnr/de1_audio/makefile new file mode 100644 index 0000000..0a8636c --- /dev/null +++ b/pnr/de1_audio/makefile @@ -0,0 +1,16 @@ +SIM_PROJECT_NAME = de1_audio +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile + + |