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| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
118 files changed, 11175 insertions, 0 deletions
diff --git a/doc/datasheet.yaml b/doc/datasheet.yaml new file mode 100644 index 0000000..a8aae06 --- /dev/null +++ b/doc/datasheet.yaml @@ -0,0 +1,26 @@ +--- +title: Pulse Width Modulator +subtitle: Datasheet +author: J Färber +date: April 2022 +lang: en-UK +geometry: a4paper, left=25mm, right=20mm, top=20mm, bottom=25mm +fontsize: 12pt +code-block-font-size: \scriptsize +titlepage: true +logo: images/uasa-logo.pdf +#toc: true +#lof: true +#lot: true +#toc-own-page: true +colorlinks: true +secnumdepth: 4 +header-includes: +# 4th level header rendering +# see https://stackoverflow.com/questions/21198025/pandoc-generation-of-pdf-from-markdown-4th-header-is-rendered-differently/21204829#21204829 + - | + ``` {=latex} + \let\originAlParaGraph\paragraph + \renewcommand{\paragraph}[1]{\originAlParaGraph{#1} \hfill} + ``` +--- diff --git a/doc/images/uasa-logo.pdf b/doc/images/uasa-logo.pdf new file mode 100644 index 0000000..6ad508e --- /dev/null +++ b/doc/images/uasa-logo.pdf @@ -0,0 +1,2737 @@ +%PDF-1.3
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diff --git a/doc/makefile b/doc/makefile new file mode 100644 index 0000000..ac16ff2 --- /dev/null +++ b/doc/makefile @@ -0,0 +1,78 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating documentation process +## based on markdown and pandoc +## +## ---------------------------------------------------------------------------- + +################################################################### +# Definitions +# +################################################################### +PROJECT = pulse_width_modulator + +DATASHEET_YAML = datasheet.yaml +REPORT_YAML = report.yaml +PRESENTATION_YAML = presentation.yaml + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make datasheet" to create a datasheet' + @echo ' "make report" to create a report' + @echo ' "make presentation" to create a presentation' + @echo ' "make clean" to remove all generated files' + + +datasheet: $(PROJECT)_datasheet.md + pandoc --template uasa_meng_vlsi_template.tex $(DATASHEET_YAML) $(PROJECT)_datasheet.md -o $(PROJECT)_datasheet.pdf --highlight-style tango + + +report: $(PROJECT)_report.md + pandoc --template uasa_meng_vlsi_template.tex $(REPORT_YAML) $(PROJECT)_report.md -o $(PROJECT)_report.pdf --highlight-style tango --number-sections + + +presentation: $(PROJECT)_presentation.md + pandoc -t beamer --template uasa_meng_vlsi_template.tex $(PRESENTATION_YAML) $(PROJECT)_presentation.md -o $(PROJECT)_presentation.pdf + + + +clean: + rm -rf $(PROJECT)_datasheet.pdf $(PROJECT)_report.pdf $(PROJECT)_presentation.pdf + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## project +## | +## |-- makefile +## | +## +-- doc/ +## | |-- stepper_motor_controller_datasheet.md +## | |-- stepper_motor_controller_datasheet.pdf +## | |-- stepper_motor_controller_report.md +## | |-- stepper_motor_controller_report.pdf +## | |-- stepper_motor_controller_presentation.md +## | |-- stepper_motor_controller_presentation.pdf +## | |-- ... +## | | +## | +-- images +## | |-- smctrl_modes.fodg +## | |-- smctrl_modes.png +## | |-- smctrl_modes_simwave.png +## | |-- wave_drive_timing.pdf +## | |-- wave_drive_timing.svg +## | |-- ... +## | +## ---------------------------------------------------------------------------- + diff --git a/doc/presentation.yaml b/doc/presentation.yaml new file mode 100644 index 0000000..fbb54bf --- /dev/null +++ b/doc/presentation.yaml @@ -0,0 +1,11 @@ +--- +title: Presentation Title +subtitle: VLSI-Design Module - Presentation +author: J Färber +date: July 202x +lang: en-UK +theme: Pittsburgh +colortheme: default +code-block-font-size: \tiny +--- + diff --git a/doc/pulse_width_modulator_datasheet.md b/doc/pulse_width_modulator_datasheet.md new file mode 100644 index 0000000..2f1caa4 --- /dev/null +++ b/doc/pulse_width_modulator_datasheet.md @@ -0,0 +1,206 @@ +Introduction +============ + +A heartbeat generator can be used in a digital system to ... + +Features +======== + +Normal rhythm produces four entities – a P wave, a QRS complex, a T wave, and a U wave – that each +have a fairly unique pattern. [[1]](https://en.wikipedia.org/wiki/Electrocardiography) + +For simplicity the existing heartbeat module generates the QRS complex and T wave only. + + * Models QRS-Complex and T-Wave + * Average time values based on 72 bpm + * Enable input for external prescaler + + +General Description +=================== + +{width=40%} + +| **Name** | **Type** | **Direction** | **Polarity** | **Description** | +|-------------|-------------------|:-------------:|:------------:|-----------------| +| clk_i | std_ulogic | IN | HIGH | clock | + +: Heartbeat Generator - Description of I/O Signals + + +Functional Description +====================== + +The shape of an [electrogardiogramm](https://en.wikipedia.org/wiki/Electrocardiography) as a voltage graph over time + + + +{width=20%} + +The important QRS complex and T wave are modelled as digital pulses. + +{width=80%} + + +Design Description +================== + +A conceptional RTL diagram is shown below. + +{width=60%} + +The simulation result shows two full periods based on a clock period of 1 ms + +{width=80%} + +In more detail using cursors to display correct parameters of the QRS complex and T wave. + +{width=80%} + + + +Device Utilization and Performance +================================== + +The following table shows the utilisation of both modules heartbeat_gen and cntdnmodm. + +The following results are extracted from + + ```pure + pnr/de1_heartbeat_gen/de1_heartbeat_gen.fit.rpt + ``` + + +```pure ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +``` + +The following results are extracted from + + ```pure +de1_heartbeat_gen.sta.rpt +``` + +```pure ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ + +-----------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+ + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ + +``` + +Application Note +================ + +The following test environment on a DE1 prototype board uses a system clock frequency of 50 MHz. +A prescaler is parameterised to generate an output signal with a period of 1 ms. + +{width=70%} + + + +Appendix +======== + +References +---------- + +* [Wiki: Electrocardiography](https://en.wikipedia.org/wiki/Electrocardiography) + +Project Hierarchy +----------------- + +### Module Hierarchy for Verification + +```pure +t_heartbeat_gen(tbench) + heartbeat_gen(rtl) +``` + +### Prototype Environment + +```pure +de1_heartbeat_gen(structure) + heartbeat_gen(rtl) + cntdnmodm(rtl) +``` + +VHDL Sources +------------ + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY heartbeat_gen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector; + heartbeat_o : OUT std_ulogic + ); +END heartbeat_gen; +``` + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ARCHITECTURE rtl OF heartbeat_gen IS + + CONSTANT n : natural := 10; + CONSTANT zero : unsigned(n-1 DOWNTO 0) := (OTHERS => '0'); + + CONSTANT heartbeat_period : unsigned(n-1 DOWNTO 0) := to_unsigned(833, n); + CONSTANT qrs_width : unsigned(n-1 DOWNTO 0) := to_unsigned(100, n); + CONSTANT st_width + CONSTANT t_width + CONSTANT qt_width + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + + SIGNAL tc_qrs : std_ulogic; -- qrs interval + SIGNAL tc_t : std_ulogic; -- T wave + +BEGIN + + next_state_logic : + + + + state_register : + + + -- output_logic + t_wave : tc_t <= + + + + qrs_complex : tc_qrs <= + + + output_value : heartbeat_o <= + + +END rtl; +``` + +Revision History +---------------- + +| **Date** | **Version** | **Change Summary** | +|:----------|:-------------|:--------------------| +| May 2020 | 0.1 | Initial Release | +| April 2021 | 0.2 | Added parameterisation | + diff --git a/doc/pulse_width_modulator_presentation.md b/doc/pulse_width_modulator_presentation.md new file mode 100644 index 0000000..d742c03 --- /dev/null +++ b/doc/pulse_width_modulator_presentation.md @@ -0,0 +1,106 @@ +--- +title: Heartbeat Generator +subtitle: VLSI-Design Module - Presentation +author: J Färber +date: SS2021 +--- + +Overview +======== + +* Features +* Interface Signals +* Block Diagram +* Functional Description +* Simulation Result +* Device Utilization and Performance +* Demonstration +* Questions + +Features +======== + + * Models QRS-Complex and T-Wave + * Average time values based on 72 bpm + * Enable input for external prescaler + +Interface Signals +================= + +{width=40%} + + +Functional Description +====================== + +Simplification to Digital Pulses +--------- + +{width=20%} + + +{width=80%} + + +Functional Description +====================== + +Conceptional RTL Diagram +--------------- + +{width=60%} + +Simulation Result - Top Level +============================= + +{width=80%} + +Device Utilization and Performance +================================== + +```pure ++------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-----------------------------------------+ +; Fitter Status ; Successful - Wed Mar 31 11:50:15 2021 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web ; +; Revision Name ; de1_heartbeat_gen ; +; Top-level Entity Name ; de1_heartbeat_gen ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 50 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 50 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 26 / 18,752 ( < 1 % ) ; +; Total registers ; 26 ; +; Total pins ; 15 / 315 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-----------------------------------------+ +``` + +Demonstration +============= + +Prototype Setup +--------------- + +{width=70%} + +Demonstration +============= + +Test Environment +---------------- + + + + + +Questions +========= + +Thank you for your attention ! + diff --git a/doc/pulse_width_modulator_report.md b/doc/pulse_width_modulator_report.md new file mode 100644 index 0000000..67cb4c2 --- /dev/null +++ b/doc/pulse_width_modulator_report.md @@ -0,0 +1,235 @@ +Introduction +============ + +A heartbeat generator can be used in a digital system to display activity of a system. +Based on population studies, a heartrate between 60 and 100 beats per minute (bpm) +is considered as normal for a human adult. + +Features +======== + +Normal rhythm produces four entities – a P wave, a QRS complex, a T wave, and a U wave – that each +have a fairly unique pattern. [[1]](https://en.wikipedia.org/wiki/Electrocardiography) + +For simplicity the existing heartbeat modules generates the QRS complex and T wave only. + + * Models QRS-Complex and T-Wave + * Average time values based on 72 bpm + * Enable input for external prescaler + + +General Description +=================== + +{width=40%} + +| **Name** | **Type** | **Direction** | **Polarity** | **Description** | +|-------------|-------------------|:-------------:|:------------:|-----------------| +| clk_i | std_ulogic | IN | HIGH | clock | +| rst_ni | std_ulogic | IN | LOW | reset | +| en_pi | std_ulogic | IN | HIGH | enable | +| count_o | std_ulogic_vector | OUT | HIGH | count value | +| heartbeat_o | std_ulogic | OUT | HIGH | hearbeat pulse output | + +: Heartbeat Generator - Description of I/O Signals + + +Functional Description +====================== + +The shape of an [electrogardiogramm](https://en.wikipedia.org/wiki/Electrocardiography) as a voltage graph over time + + + +{width=20%} + +The important QRS complex and T wave are modelled as digital pulses. + +{width=80%} + + +Design Description +================== + +A conceptional RTL diagram is shown below. + +{width=60%} + +The simulation result shows two full periods based on a clock period of 1 ms + +{width=80%} + +In more detail using cursors to display correct parameters of the QRS complex and T wave. + +{width=80%} + + + +Device Utilization and Performance +================================== + +The following table shows the utilisation of both modules heartbeat_gen and cntdnmodm. + +```pure ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Wed Mar 31 11:50:15 2021 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; de1_heartbeat_gen ; +; Top-level Entity Name ; de1_heartbeat_gen ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 50 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 50 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 26 / 18,752 ( < 1 % ) ; +; Total registers ; 26 ; +; Total pins ; 15 / 315 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ +``` + +```pure + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; de1_heartbeat_gen ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + +-----------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; ++------------+------+--------+-----------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; ++------------+------+--------+-----------+ + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 3.390 ; 0.241 ; 13.381 ; 3.796 ; 8.889 ; +; CLOCK_50 ; 3.390 ; 0.241 ; 13.381 ; 3.796 ; 8.889 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ +``` + +Application Note +================ + +The following test environment on a DE1 prototype board uses a system clock frequency of 50 MHz. +A prescaler is parameterised to generate an output signal with a period of 1 ms. + +{width=70%} + + + +Appendix +======== + +References +---------- + +* [Wiki: Electrocardiography](https://en.wikipedia.org/wiki/Electrocardiography) + +Project Hierarchy +----------------- + +### Module Hierarchy for Verification + +```pure +t_heartbeat_gen(tbench) + heartbeat_gen(rtl) +``` + +### Prototype Environment + +```pure +de1_heartbeat_gen(structure) + heartbeat_gen(rtl) + cntdnmodm(rtl) +``` + +VHDL Sources +------------ + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY heartbeat_gen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector; + heartbeat_o : OUT std_ulogic + ); +END heartbeat_gen; +``` + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ARCHITECTURE rtl OF heartbeat_gen IS + + CONSTANT n : natural := 10; + CONSTANT zero : unsigned(n-1 DOWNTO 0) := (OTHERS => '0'); + + CONSTANT heartbeat_period : unsigned(n-1 DOWNTO 0) := to_unsigned(833, n); + CONSTANT qrs_width : unsigned(n-1 DOWNTO 0) := to_unsigned(100, n); + CONSTANT st_width + CONSTANT t_width + CONSTANT qt_width + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + + SIGNAL tc_qrs : std_ulogic; -- qrs interval + SIGNAL tc_t : std_ulogic; -- T wave + +BEGIN + + next_state_logic : + + + + state_register : + + + -- output_logic + t_wave : tc_t <= + + + + qrs_complex : tc_qrs <= + + + output_value : heartbeat_o <= + + +END rtl; +``` + +Revision History +---------------- + +| **Date** | **Version** | **Change Summary** | +|:----------|:-------------|:--------------------| +| May 2020 | 0.1 | Initial Release | +| April 2021 | 0.2 | Added parameterisation | + diff --git a/doc/report.yaml b/doc/report.yaml new file mode 100644 index 0000000..1989e0a --- /dev/null +++ b/doc/report.yaml @@ -0,0 +1,27 @@ +--- +title: Pulse Width Modulator +subtitle: VLSI-Design Module - Report +author: J Färber +date: SS2022 +lang: en-UK +geometry: a4paper, left=25mm, right=20mm, top=20mm, bottom=25mm +fontsize: 12pt +code-block-font-size: \scriptsize +titlepage: true +logo: images/uasa-logo.pdf +toc: true +lof: true +lot: true +toc-own-page: true +colorlinks: true +secnumdepth: 4 +header-includes: +# 4th level header rendering +# see https://stackoverflow.com/questions/21198025/pandoc-generation-of-pdf-from-markdown-4th-header-is-rendered-differently/21204829#21204829 + - | + ``` {=latex} + \let\originAlParaGraph\paragraph + \renewcommand{\paragraph}[1]{\originAlParaGraph{#1} \hfill} + ``` +--- + diff --git a/doc/uasa_meng_vlsi_template.tex b/doc/uasa_meng_vlsi_template.tex new file mode 100644 index 0000000..7aac2a7 --- /dev/null +++ b/doc/uasa_meng_vlsi_template.tex @@ -0,0 +1,1038 @@ +%% +% Copyright (c) 2017 - 2020, Pascal Wagler; +% Copyright (c) 2014 - 2020, John MacFarlane +% +% All rights reserved. +% +% Redistribution and use in source and binary forms, with or without +% modification, are permitted provided that the following conditions +% are met: +% +% - Redistributions of source code must retain the above copyright +% notice, this list of conditions and the following disclaimer. +% +% - Redistributions in binary form must reproduce the above copyright +% notice, this list of conditions and the following disclaimer in the +% documentation and/or other materials provided with the distribution. +% +% - Neither the name of John MacFarlane nor the names of other +% contributors may be used to endorse or promote products derived +% from this software without specific prior written permission. +% +% THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +% "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +% LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +% FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +% COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +% INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +% BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +% LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +% CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +% LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +% ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +% POSSIBILITY OF SUCH DAMAGE. +%% + +%% +% This is the Eisvogel pandoc LaTeX template. +% +% For usage information and examples visit the official GitHub page: +% https://github.com/Wandmalfarbe/pandoc-latex-template +%% + +% Options for packages loaded elsewhere +\PassOptionsToPackage{unicode$for(hyperrefoptions)$,$hyperrefoptions$$endfor$}{hyperref} +\PassOptionsToPackage{hyphens}{url} +\PassOptionsToPackage{dvipsnames,svgnames*,x11names*,table}{xcolor} +$if(dir)$ +$if(latex-dir-rtl)$ +\PassOptionsToPackage{RTLdocument}{bidi} +$endif$ +$endif$ +% +\documentclass[ +$if(fontsize)$ + $fontsize$, +$endif$ +$if(lang)$ + $babel-lang$, +$endif$ +$if(papersize)$ + $papersize$paper, +$else$ + a4paper, +$endif$ +$if(beamer)$ + ignorenonframetext, +$if(handout)$ + handout, +$endif$ +$if(aspectratio)$ + aspectratio=$aspectratio$, +$endif$ +$endif$ +$for(classoption)$ + $classoption$$sep$, +$endfor$ +,tablecaptionabove +]{$if(beamer)$$documentclass$$else$$if(book)$scrbook$else$scrartcl$endif$$endif$} +$if(beamer)$ +$if(background-image)$ +\usebackgroundtemplate{% + \includegraphics[width=\paperwidth]{$background-image$}% +} +$endif$ +\usepackage{pgfpages} +\setbeamertemplate{caption}[numbered] +\setbeamertemplate{caption label separator}{: } +\setbeamercolor{caption name}{fg=normal text.fg} +\beamertemplatenavigationsymbols$if(navigation)$$navigation$$else$empty$endif$ +$for(beameroption)$ +\setbeameroption{$beameroption$} +$endfor$ +% Prevent slide breaks in the middle of a paragraph +\widowpenalties 1 10000 +\raggedbottom +$if(section-titles)$ +\setbeamertemplate{part page}{ + \centering + \begin{beamercolorbox}[sep=16pt,center]{part title} + \usebeamerfont{part title}\insertpart\par + \end{beamercolorbox} +} +\setbeamertemplate{section page}{ + \centering + \begin{beamercolorbox}[sep=12pt,center]{part title} + \usebeamerfont{section title}\insertsection\par + \end{beamercolorbox} +} +\setbeamertemplate{subsection page}{ + \centering + \begin{beamercolorbox}[sep=8pt,center]{part title} + \usebeamerfont{subsection title}\insertsubsection\par + \end{beamercolorbox} +} +\AtBeginPart{ + \frame{\partpage} +} +\AtBeginSection{ + \ifbibliography + \else + \frame{\sectionpage} + \fi +} +\AtBeginSubsection{ + \frame{\subsectionpage} +} +$endif$ +$endif$ +$if(beamerarticle)$ +\usepackage{beamerarticle} % needs to be loaded first +$endif$ +$if(fontfamily)$ +\usepackage[$for(fontfamilyoptions)$$fontfamilyoptions$$sep$,$endfor$]{$fontfamily$} +$else$ +\usepackage{lmodern} +$endif$ +$if(linestretch)$ +\usepackage{setspace} +\setstretch{$linestretch$} +$else$ +\usepackage{setspace} +\setstretch{1.2} +$endif$ +\usepackage{amssymb,amsmath} +\usepackage{ifxetex,ifluatex} +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + \usepackage[$if(fontenc)$$fontenc$$else$T1$endif$]{fontenc} + \usepackage[utf8]{inputenc} + \usepackage{textcomp} % provide euro and other symbols +\else % if luatex or xetex +$if(mathspec)$ + \ifxetex + \usepackage{mathspec} + \else + \usepackage{unicode-math} + \fi +$else$ + \usepackage{unicode-math} +$endif$ + \defaultfontfeatures{Scale=MatchLowercase} + \defaultfontfeatures[\rmfamily]{Ligatures=TeX,Scale=1} +$if(mainfont)$ + \setmainfont[$for(mainfontoptions)$$mainfontoptions$$sep$,$endfor$]{$mainfont$} +$endif$ +$if(sansfont)$ + \setsansfont[$for(sansfontoptions)$$sansfontoptions$$sep$,$endfor$]{$sansfont$} +$endif$ +$if(monofont)$ + \setmonofont[$for(monofontoptions)$$monofontoptions$$sep$,$endfor$]{$monofont$} +$endif$ +$for(fontfamilies)$ + \newfontfamily{$fontfamilies.name$}[$for(fontfamilies.options)$$fontfamilies.options$$sep$,$endfor$]{$fontfamilies.font$} +$endfor$ +$if(mathfont)$ +$if(mathspec)$ + \ifxetex + \setmathfont(Digits,Latin,Greek)[$for(mathfontoptions)$$mathfontoptions$$sep$,$endfor$]{$mathfont$} + \else + \setmathfont[$for(mathfontoptions)$$mathfontoptions$$sep$,$endfor$]{$mathfont$} + \fi +$else$ + \setmathfont[$for(mathfontoptions)$$mathfontoptions$$sep$,$endfor$]{$mathfont$} +$endif$ +$endif$ +$if(CJKmainfont)$ + \ifxetex + \usepackage{xeCJK} + \setCJKmainfont[$for(CJKoptions)$$CJKoptions$$sep$,$endfor$]{$CJKmainfont$} + \fi +$endif$ +$if(luatexjapresetoptions)$ + \ifluatex + \usepackage[$for(luatexjapresetoptions)$$luatexjapresetoptions$$sep$,$endfor$]{luatexja-preset} + \fi +$endif$ +$if(CJKmainfont)$ + \ifluatex + \usepackage[$for(luatexjafontspecoptions)$$luatexjafontspecoptions$$sep$,$endfor$]{luatexja-fontspec} + \setmainjfont[$for(CJKoptions)$$CJKoptions$$sep$,$endfor$]{$CJKmainfont$} + \fi +$endif$ +\fi +$if(beamer)$ +$if(theme)$ +\usetheme[$for(themeoptions)$$themeoptions$$sep$,$endfor$]{$theme$} +$endif$ +$if(colortheme)$ +\usecolortheme{$colortheme$} +$endif$ +$if(fonttheme)$ +\usefonttheme{$fonttheme$} +$endif$ +$if(mainfont)$ +\usefonttheme{serif} % use mainfont rather than sansfont for slide text +$endif$ +$if(innertheme)$ +\useinnertheme{$innertheme$} +$endif$ +$if(outertheme)$ +\useoutertheme{$outertheme$} +$endif$ +$endif$ +% Use upquote if available, for straight quotes in verbatim environments +\IfFileExists{upquote.sty}{\usepackage{upquote}}{} +\IfFileExists{microtype.sty}{% use microtype if available + \usepackage[$for(microtypeoptions)$$microtypeoptions$$sep$,$endfor$]{microtype} + \UseMicrotypeSet[protrusion]{basicmath} % disable protrusion for tt fonts +}{} +$if(indent)$ +$else$ +\makeatletter +\@ifundefined{KOMAClassName}{% if non-KOMA class + \IfFileExists{parskip.sty}{% + \usepackage{parskip} + }{% else + \setlength{\parindent}{0pt} + \setlength{\parskip}{6pt plus 2pt minus 1pt}} +}{% if KOMA class + \KOMAoptions{parskip=half}} +\makeatother +$endif$ +$if(verbatim-in-note)$ +\usepackage{fancyvrb} +$endif$ +\usepackage{xcolor} +\definecolor{default-linkcolor}{HTML}{A50000} +\definecolor{default-filecolor}{HTML}{A50000} +\definecolor{default-citecolor}{HTML}{4077C0} +\definecolor{default-urlcolor}{HTML}{4077C0} +\IfFileExists{xurl.sty}{\usepackage{xurl}}{} % add URL line breaks if available +$if(footnotes-pretty)$ +% load footmisc in order to customize footnotes (footmisc has to be loaded before hyperref, cf. https://tex.stackexchange.com/a/169124/144087) +\usepackage[hang,flushmargin,bottom,multiple]{footmisc} +\setlength{\footnotemargin}{0.8em} % set space between footnote nr and text +\setlength{\footnotesep}{\baselineskip} % set space between multiple footnotes +\setlength{\skip\footins}{0.3cm} % set space between page content and footnote +\setlength{\footskip}{0.9cm} % set space between footnote and page bottom +$endif$ +\IfFileExists{bookmark.sty}{\usepackage{bookmark}}{\usepackage{hyperref}} +\hypersetup{ +$if(title-meta)$ + pdftitle={$title-meta$}, +$endif$ +$if(author-meta)$ + pdfauthor={$author-meta$}, +$endif$ +$if(lang)$ + pdflang={$lang$}, +$endif$ +$if(subject)$ + pdfsubject={$subject$}, +$endif$ +$if(keywords)$ + pdfkeywords={$for(keywords)$$keywords$$sep$, $endfor$}, +$endif$ +$if(colorlinks)$ + colorlinks=true, + linkcolor=$if(linkcolor)$$linkcolor$$else$default-linkcolor$endif$, + filecolor=$if(filecolor)$$filecolor$$else$default-filecolor$endif$, + citecolor=$if(citecolor)$$citecolor$$else$default-citecolor$endif$, + urlcolor=$if(urlcolor)$$urlcolor$$else$default-urlcolor$endif$, +$else$ + hidelinks, +$endif$ + breaklinks=true, + pdfcreator={LaTeX via pandoc with the Eisvogel template}} +\urlstyle{same} % disable monospaced font for URLs +$if(verbatim-in-note)$ +\VerbatimFootnotes % allow verbatim text in footnotes +$endif$ +$if(geometry)$ +$if(beamer)$ +\geometry{$for(geometry)$$geometry$$sep$,$endfor$} +$else$ +\usepackage[$for(geometry)$$geometry$$sep$,$endfor$]{geometry} +$endif$ +$else$ +$if(beamer)$ +$else$ +\usepackage[margin=2.5cm,includehead=true,includefoot=true,centering,$for(geometry)$$geometry$$sep$,$endfor$]{geometry} +$endif$ +$endif$ +$if(logo)$ +\usepackage[export]{adjustbox} +\usepackage{graphicx} +$endif$ +$if(beamer)$ +\newif\ifbibliography +$endif$ +$if(listings)$ +\usepackage{listings} +\newcommand{\passthrough}[1]{#1} +\lstset{defaultdialect=[5.3]Lua} +\lstset{defaultdialect=[x86masm]Assembler} +$endif$ +$if(listings-no-page-break)$ +\usepackage{etoolbox} +\BeforeBeginEnvironment{lstlisting}{\par\noindent\begin{minipage}{\linewidth}} +\AfterEndEnvironment{lstlisting}{\end{minipage}\par\addvspace{\topskip}} +$endif$ +$if(lhs)$ +\lstnewenvironment{code}{\lstset{language=Haskell,basicstyle=\small\ttfamily}}{} +$endif$ +$if(highlighting-macros)$ +$highlighting-macros$ + +% Workaround/bugfix from jannick0. +% See https://github.com/jgm/pandoc/issues/4302#issuecomment-360669013) +% or https://github.com/Wandmalfarbe/pandoc-latex-template/issues/2 +% +% Redefine the verbatim environment 'Highlighting' to break long lines (with +% the help of fvextra). Redefinition is necessary because it is unlikely that +% pandoc includes fvextra in the default template. +\usepackage{fvextra} +\DefineVerbatimEnvironment{Highlighting}{Verbatim}{breaklines,fontsize=$if(code-block-font-size)$$code-block-font-size$$else$\small$endif$,commandchars=\\\{\}} + +$endif$ +$if(tables)$ +\usepackage{longtable,booktabs} +$if(beamer)$ +\usepackage{caption} +% Make caption package work with longtable +\makeatletter +\def\fnum@table{\tablename~\thetable} +\makeatother +$else$ +% Correct order of tables after \paragraph or \subparagraph +\usepackage{etoolbox} +\makeatletter +\patchcmd\longtable{\par}{\if@noskipsec\mbox{}\fi\par}{}{} +\makeatother +% Allow footnotes in longtable head/foot +\IfFileExists{footnotehyper.sty}{\usepackage{footnotehyper}}{\usepackage{footnote}} +\makesavenoteenv{longtable} +$endif$ +$endif$ +% add backlinks to footnote references, cf. https://tex.stackexchange.com/questions/302266/make-footnote-clickable-both-ways +$if(footnotes-disable-backlinks)$ +$else$ +\usepackage{footnotebackref} +$endif$ +$if(graphics)$ +\usepackage{graphicx,grffile} +\makeatletter +\def\maxwidth{\ifdim\Gin@nat@width>\linewidth\linewidth\else\Gin@nat@width\fi} +\def\maxheight{\ifdim\Gin@nat@height>\textheight\textheight\else\Gin@nat@height\fi} +\makeatother +% Scale images if necessary, so that they will not overflow the page +% margins by default, and it is still possible to overwrite the defaults +% using explicit options in \includegraphics[width, height, ...]{} +\setkeys{Gin}{width=\maxwidth,height=\maxheight,keepaspectratio} +$endif$ +$if(links-as-notes)$ +% Make links footnotes instead of hotlinks: +\DeclareRobustCommand{\href}[2]{#2\footnote{\url{#1}}} +$endif$ +$if(strikeout)$ +\usepackage[normalem]{ulem} +% Avoid problems with \sout in headers with hyperref +\pdfstringdefDisableCommands{\renewcommand{\sout}{}} +$endif$ +\setlength{\emergencystretch}{3em} % prevent overfull lines +\providecommand{\tightlist}{% + \setlength{\itemsep}{0pt}\setlength{\parskip}{0pt}} +$if(numbersections)$ +\setcounter{secnumdepth}{$if(secnumdepth)$$secnumdepth$$else$3$endif$} +$else$ +\setcounter{secnumdepth}{-\maxdimen} % remove section numbering +$endif$ +$if(beamer)$ +$else$ +$if(block-headings)$ +% Make \paragraph and \subparagraph free-standing +\ifx\paragraph\undefined\else + \let\oldparagraph\paragraph + \renewcommand{\paragraph}[1]{\oldparagraph{#1}\mbox{}} +\fi +\ifx\subparagraph\undefined\else + \let\oldsubparagraph\subparagraph + \renewcommand{\subparagraph}[1]{\oldsubparagraph{#1}\mbox{}} +\fi +$endif$ +$endif$ +$if(pagestyle)$ +\pagestyle{$pagestyle$} +$endif$ + +% Make use of float-package and set default placement for figures to H. +% The option H means 'PUT IT HERE' (as opposed to the standard h option which means 'You may put it here if you like'). +\usepackage{float} +\floatplacement{figure}{$if(float-placement-figure)$$float-placement-figure$$else$H$endif$} + +$for(header-includes)$ +$header-includes$ +$endfor$ +$if(lang)$ +\ifxetex + $if(mainfont)$ + $else$ + % See issue https://github.com/reutenauer/polyglossia/issues/127 + \renewcommand*\familydefault{\sfdefault} + $endif$ + % Load polyglossia as late as possible: uses bidi with RTL langages (e.g. Hebrew, Arabic) + \usepackage{polyglossia} + \setmainlanguage[$polyglossia-lang.options$]{$polyglossia-lang.name$} +$for(polyglossia-otherlangs)$ + \setotherlanguage[$polyglossia-otherlangs.options$]{$polyglossia-otherlangs.name$} +$endfor$ +\else + \usepackage[shorthands=off,$for(babel-otherlangs)$$babel-otherlangs$,$endfor$main=$babel-lang$]{babel} +$if(babel-newcommands)$ + $babel-newcommands$ +$endif$ +\fi +$endif$ +$if(dir)$ +\ifxetex + % Load bidi as late as possible as it modifies e.g. graphicx + \usepackage{bidi} +\fi +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + \TeXXeTstate=1 + \newcommand{\RL}[1]{\beginR #1\endR} + \newcommand{\LR}[1]{\beginL #1\endL} + \newenvironment{RTL}{\beginR}{\endR} + \newenvironment{LTR}{\beginL}{\endL} +\fi +$endif$ +$if(natbib)$ +\usepackage[$natbiboptions$]{natbib} +\bibliographystyle{$if(biblio-style)$$biblio-style$$else$plainnat$endif$} +$endif$ +$if(biblatex)$ +\usepackage[$if(biblio-style)$style=$biblio-style$,$endif$$for(biblatexoptions)$$biblatexoptions$$sep$,$endfor$]{biblatex} +$for(bibliography)$ +\addbibresource{$bibliography$} +$endfor$ +$endif$ +$if(csl-refs)$ +\newlength{\cslhangindent} +\setlength{\cslhangindent}{1.5em} +\newenvironment{cslreferences}% + {$if(csl-hanging-indent)$\setlength{\parindent}{0pt}% + \everypar{\setlength{\hangindent}{\cslhangindent}}\ignorespaces$endif$}% + {\par} +$endif$ + +$if(title)$ +\title{$title$$if(thanks)$\thanks{$thanks$}$endif$} +$endif$ +$if(subtitle)$ +$if(beamer)$ +$else$ +\usepackage{etoolbox} +\makeatletter +\providecommand{\subtitle}[1]{% add subtitle to \maketitle + \apptocmd{\@title}{\par {\large #1 \par}}{}{} +} +\makeatother +$endif$ +\subtitle{$subtitle$} +$endif$ +$if(author)$ +\author{$for(author)$$author$$sep$ \and $endfor$} +$endif$ +\date{$date$} +$if(beamer)$ +$if(institute)$ +\institute{$for(institute)$$institute$$sep$ \and $endfor$} +$endif$ +$if(titlegraphic)$ +\titlegraphic{\includegraphics{$titlegraphic$}} +$endif$ +$if(logo)$ +\logo{\includegraphics{$logo$}} +$endif$ +$endif$ + + + +%% +%% added +%% + +% +% language specification +% +% If no language is specified, use English as the default main document language. +% +$if(lang)$$else$ +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + \usepackage[shorthands=off,$for(babel-otherlangs)$$babel-otherlangs$,$endfor$main=english]{babel} +$if(babel-newcommands)$ + $babel-newcommands$ +$endif$ +\else + $if(mainfont)$ + $else$ + % Workaround for bug in Polyglossia that breaks `\familydefault` when `\setmainlanguage` is used. + % See https://github.com/Wandmalfarbe/pandoc-latex-template/issues/8 + % See https://github.com/reutenauer/polyglossia/issues/186 + % See https://github.com/reutenauer/polyglossia/issues/127 + \renewcommand*\familydefault{\sfdefault} + $endif$ + % load polyglossia as late as possible as it *could* call bidi if RTL lang (e.g. Hebrew or Arabic) + \usepackage{polyglossia} + \setmainlanguage[]{english} +$for(polyglossia-otherlangs)$ + \setotherlanguage[$polyglossia-otherlangs.options$]{$polyglossia-otherlangs.name$} +$endfor$ +\fi +$endif$ + +$if(page-background)$ +\usepackage[pages=all]{background} +$endif$ + +% +% for the background color of the title page +% +$if(titlepage)$ +\usepackage{pagecolor} +\usepackage{afterpage} +$if(titlepage-background)$ +\usepackage{tikz} +$endif$ +$if(geometry)$ +$else$ +\usepackage[margin=2.5cm,includehead=true,includefoot=true,centering]{geometry} +$endif$ +$endif$ + +% +% break urls +% +\PassOptionsToPackage{hyphens}{url} + +% +% When using babel or polyglossia with biblatex, loading csquotes is recommended +% to ensure that quoted texts are typeset according to the rules of your main language. +% +\usepackage{csquotes} + +% +% captions +% +\definecolor{caption-color}{HTML}{777777} +$if(beamer)$ +$else$ +\usepackage[font={stretch=1.2}, textfont={color=caption-color}, position=top, skip=4mm, labelfont=bf, singlelinecheck=false, justification=$if(caption-justification)$$caption-justification$$else$raggedright$endif$]{caption} +\setcapindent{0em} +$endif$ + +% +% blockquote +% +\definecolor{blockquote-border}{RGB}{221,221,221} +\definecolor{blockquote-text}{RGB}{119,119,119} +\usepackage{mdframed} +\newmdenv[rightline=false,bottomline=false,topline=false,linewidth=3pt,linecolor=blockquote-border,skipabove=\parskip]{customblockquote} +\renewenvironment{quote}{\begin{customblockquote}\list{}{\rightmargin=0em\leftmargin=0em}% +\item\relax\color{blockquote-text}\ignorespaces}{\unskip\unskip\endlist\end{customblockquote}} + +% +% Source Sans Pro as the default font family +% Source Code Pro for monospace text +% +% 'default' option sets the default +% font family to Source Sans Pro, not \sfdefault. +% +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + $if(fontfamily)$ + $else$ + \usepackage[default]{sourcesanspro} + \usepackage{sourcecodepro} + $endif$ +\else % if not pdftex + $if(mainfont)$ + $else$ + \usepackage[default]{sourcesanspro} + \usepackage{sourcecodepro} + + % XeLaTeX specific adjustments for straight quotes: https://tex.stackexchange.com/a/354887 + % This issue is already fixed (see https://github.com/silkeh/latex-sourcecodepro/pull/5) but the + % fix is still unreleased. + % TODO: Remove this workaround when the new version of sourcecodepro is released on CTAN. + \ifxetex + \makeatletter + \defaultfontfeatures[\ttfamily] + { Numbers = \sourcecodepro@figurestyle, + Scale = \SourceCodePro@scale, + Extension = .otf } + \setmonofont + [ UprightFont = *-\sourcecodepro@regstyle, + ItalicFont = *-\sourcecodepro@regstyle It, + BoldFont = *-\sourcecodepro@boldstyle, + BoldItalicFont = *-\sourcecodepro@boldstyle It ] + {SourceCodePro} + \makeatother + \fi + $endif$ +\fi + +% +% heading color +% +\definecolor{heading-color}{RGB}{40,40,40} +$if(beamer)$ +$else$ +\addtokomafont{section}{\color{heading-color}} +$endif$ +% When using the classes report, scrreprt, book, +% scrbook or memoir, uncomment the following line. +%\addtokomafont{chapter}{\color{heading-color}} + +% +% variables for title and author +% +$if(beamer)$ +$else$ +\usepackage{titling} +\title{$title$} +\author{$for(author)$$author$$sep$, $endfor$} +$endif$ + +% +% tables +% +$if(tables)$ + +\definecolor{table-row-color}{HTML}{F5F5F5} +\definecolor{table-rule-color}{HTML}{999999} + +%\arrayrulecolor{black!40} +\arrayrulecolor{table-rule-color} % color of \toprule, \midrule, \bottomrule +\setlength\heavyrulewidth{0.3ex} % thickness of \toprule, \bottomrule +\renewcommand{\arraystretch}{1.3} % spacing (padding) + +$if(table-use-row-colors)$ +% TODO: This doesn't work anymore. I don't know why. +% Reset rownum counter so that each table +% starts with the same row colors. +% https://tex.stackexchange.com/questions/170637/restarting-rowcolors +% +% Unfortunately the colored cells extend beyond the edge of the +% table because pandoc uses @-expressions (@{}) like so: +% +% \begin{longtable}[]{@{}ll@{}} +% \end{longtable} +% +% https://en.wikibooks.org/wiki/LaTeX/Tables#.40-expressions +\let\oldlongtable\longtable +\let\endoldlongtable\endlongtable +\renewenvironment{longtable}{ +\rowcolors{3}{}{table-row-color!100} % row color +\oldlongtable} { +\endoldlongtable +\global\rownum=0\relax} +$endif$ +$endif$ + +% +% remove paragraph indention +% +\setlength{\parindent}{0pt} +\setlength{\parskip}{6pt plus 2pt minus 1pt} +\setlength{\emergencystretch}{3em} % prevent overfull lines + +% +% +% Listings +% +% + +$if(listings)$ + +% +% general listing colors +% +\definecolor{listing-background}{HTML}{F7F7F7} +\definecolor{listing-rule}{HTML}{B3B2B3} +\definecolor{listing-numbers}{HTML}{B3B2B3} +\definecolor{listing-text-color}{HTML}{000000} +\definecolor{listing-keyword}{HTML}{435489} +\definecolor{listing-keyword-2}{HTML}{1284CA} % additional keywords +\definecolor{listing-keyword-3}{HTML}{9137CB} % additional keywords +\definecolor{listing-identifier}{HTML}{435489} +\definecolor{listing-string}{HTML}{00999A} +\definecolor{listing-comment}{HTML}{8E8E8E} + +\lstdefinestyle{eisvogel_listing_style}{ + language = java, +$if(listings-disable-line-numbers)$ + xleftmargin = 0.6em, + framexleftmargin = 0.4em, +$else$ + numbers = left, + xleftmargin = 2.7em, + framexleftmargin = 2.5em, +$endif$ + backgroundcolor = \color{listing-background}, + basicstyle = \color{listing-text-color}\linespread{1.0}$if(code-block-font-size)$$code-block-font-size$$else$\small$endif$\ttfamily{}, + breaklines = true, + frame = single, + framesep = 0.19em, + rulecolor = \color{listing-rule}, + frameround = ffff, + tabsize = 4, + numberstyle = \color{listing-numbers}, + aboveskip = 1.0em, + belowskip = 0.1em, + abovecaptionskip = 0em, + belowcaptionskip = 1.0em, + keywordstyle = {\color{listing-keyword}\bfseries}, + keywordstyle = {[2]\color{listing-keyword-2}\bfseries}, + keywordstyle = {[3]\color{listing-keyword-3}\bfseries\itshape}, + sensitive = true, + identifierstyle = \color{listing-identifier}, + commentstyle = \color{listing-comment}, + stringstyle = \color{listing-string}, + showstringspaces = false, + escapeinside = {/*@}{@*/}, % Allow LaTeX inside these special comments + literate = + {á}{{\'a}}1 {é}{{\'e}}1 {í}{{\'i}}1 {ó}{{\'o}}1 {ú}{{\'u}}1 + {Á}{{\'A}}1 {É}{{\'E}}1 {Í}{{\'I}}1 {Ó}{{\'O}}1 {Ú}{{\'U}}1 + {à}{{\`a}}1 {è}{{\'e}}1 {ì}{{\`i}}1 {ò}{{\`o}}1 {ù}{{\`u}}1 + {À}{{\`A}}1 {È}{{\'E}}1 {Ì}{{\`I}}1 {Ò}{{\`O}}1 {Ù}{{\`U}}1 + {ä}{{\"a}}1 {ë}{{\"e}}1 {ï}{{\"i}}1 {ö}{{\"o}}1 {ü}{{\"u}}1 + {Ä}{{\"A}}1 {Ë}{{\"E}}1 {Ï}{{\"I}}1 {Ö}{{\"O}}1 {Ü}{{\"U}}1 + {â}{{\^a}}1 {ê}{{\^e}}1 {î}{{\^i}}1 {ô}{{\^o}}1 {û}{{\^u}}1 + {Â}{{\^A}}1 {Ê}{{\^E}}1 {Î}{{\^I}}1 {Ô}{{\^O}}1 {Û}{{\^U}}1 + {œ}{{\oe}}1 {Œ}{{\OE}}1 {æ}{{\ae}}1 {Æ}{{\AE}}1 {ß}{{\ss}}1 + {ç}{{\c c}}1 {Ç}{{\c C}}1 {ø}{{\o}}1 {å}{{\r a}}1 {Å}{{\r A}}1 + {€}{{\EUR}}1 {£}{{\pounds}}1 {«}{{\guillemotleft}}1 + {»}{{\guillemotright}}1 {ñ}{{\~n}}1 {Ñ}{{\~N}}1 {¿}{{?`}}1 + {…}{{\ldots}}1 {≥}{{>=}}1 {≤}{{<=}}1 {„}{{\glqq}}1 {“}{{\grqq}}1 + {”}{{''}}1 +} +\lstset{style=eisvogel_listing_style} + +% +% Java (Java SE 12, 2019-06-22) +% +\lstdefinelanguage{Java}{ + morekeywords={ + % normal keywords (without data types) + abstract,assert,break,case,catch,class,continue,default, + do,else,enum,exports,extends,final,finally,for,if,implements, + import,instanceof,interface,module,native,new,package,private, + protected,public,requires,return,static,strictfp,super,switch, + synchronized,this,throw,throws,transient,try,volatile,while, + % var is an identifier + var + }, + morekeywords={[2] % data types + % primitive data types + boolean,byte,char,double,float,int,long,short, + % String + String, + % primitive wrapper types + Boolean,Byte,Character,Double,Float,Integer,Long,Short + % number types + Number,AtomicInteger,AtomicLong,BigDecimal,BigInteger,DoubleAccumulator,DoubleAdder,LongAccumulator,LongAdder,Short, + % other + Object,Void,void + }, + morekeywords={[3] % literals + % reserved words for literal values + null,true,false, + }, + sensitive, + morecomment = [l]//, + morecomment = [s]{/*}{*/}, + morecomment = [s]{/**}{*/}, + morestring = [b]", + morestring = [b]', +} + +\lstdefinelanguage{XML}{ + morestring = [b]", + moredelim = [s][\bfseries\color{listing-keyword}]{<}{\ }, + moredelim = [s][\bfseries\color{listing-keyword}]{</}{>}, + moredelim = [l][\bfseries\color{listing-keyword}]{/>}, + moredelim = [l][\bfseries\color{listing-keyword}]{>}, + morecomment = [s]{<?}{?>}, + morecomment = [s]{<!--}{-->}, + commentstyle = \color{listing-comment}, + stringstyle = \color{listing-string}, + identifierstyle = \color{listing-identifier} +} +$endif$ + +% +% header and footer +% +$if(beamer)$ +$else$ +$if(disable-header-and-footer)$ +$else$ +\usepackage{fancyhdr} + +\fancypagestyle{eisvogel-header-footer}{ + \fancyhead{} + \fancyfoot{} + \lhead[$if(header-right)$$header-right$$else$$date$$endif$]{$if(header-left)$$header-left$$else$$title$$endif$} + \chead[$if(header-center)$$header-center$$else$$endif$]{$if(header-center)$$header-center$$else$$endif$} + \rhead[$if(header-left)$$header-left$$else$$title$$endif$]{$if(header-right)$$header-right$$else$$date$$endif$} + \lfoot[$if(footer-right)$$footer-right$$else$\thepage$endif$]{$if(footer-left)$$footer-left$$else$$for(author)$$author$$sep$, $endfor$$endif$} + \cfoot[$if(footer-center)$$footer-center$$else$$endif$]{$if(footer-center)$$footer-center$$else$$endif$} + \rfoot[$if(footer-left)$$footer-left$$else$$for(author)$$author$$sep$, $endfor$$endif$]{$if(footer-right)$$footer-right$$else$\thepage$endif$} + \renewcommand{\headrulewidth}{0.4pt} + \renewcommand{\footrulewidth}{0.4pt} +} +\pagestyle{eisvogel-header-footer} +$if(page-background)$ +\backgroundsetup{ +scale=1, +color=black, +opacity=$if(page-background-opacity)$$page-background-opacity$$else$0.2$endif$, +angle=0, +contents={% + \includegraphics[width=\paperwidth,height=\paperheight]{$page-background$} + }% +} +$endif$ +$endif$ +$endif$ + +%% +%% end added +%% + +\begin{document} + +%% +%% begin titlepage +%% +$if(beamer)$ +$else$ +$if(titlepage)$ +\begin{titlepage} +$if(titlepage-background)$ +\newgeometry{top=2cm, right=4cm, bottom=3cm, left=4cm} +$else$ +\newgeometry{left=6cm} +$endif$ +$if(titlepage-color)$ +\definecolor{titlepage-color}{HTML}{$titlepage-color$} +\newpagecolor{titlepage-color}\afterpage{\restorepagecolor} +$endif$ +$if(titlepage-background)$ +\tikz[remember picture,overlay] \node[inner sep=0pt] at (current page.center){\includegraphics[width=\paperwidth,height=\paperheight]{$titlepage-background$}}; +$endif$ +\newcommand{\colorRule}[3][black]{\textcolor[HTML]{#1}{\rule{#2}{#3}}} +\begin{flushleft} +\noindent +\\[-1em] +\color[HTML]{$if(titlepage-text-color)$$titlepage-text-color$$else$5F5F5F$endif$} +\makebox[0pt][l]{\colorRule[$if(titlepage-rule-color)$$titlepage-rule-color$$else$435488$endif$]{1.3\textwidth}{$if(titlepage-rule-height)$$titlepage-rule-height$$else$4$endif$pt}} +\par +\noindent + +$if(logo)$ +\noindent +\includegraphics[width=$if(logo-width)$$logo-width$$else$100$endif$pt, right]{$logo$} +$endif$ + + +$if(titlepage-background)$ +% The titlepage with a background image has other text spacing and text size +{ + \setstretch{2} + \vfill + \vskip -8em + \noindent {\huge \textbf{\textsf{$title$}}} + $if(subtitle)$ + \vskip 1em + {\Large \textsf{$subtitle$}} + $endif$ + \vskip 2em + \noindent {\Large \textsf{$for(author)$$author$$sep$, $endfor$} \vskip 0.6em \textsf{$date$}} + \vfill +} +$else$ +{ + \setstretch{1.4} + \vfill + \noindent {\huge \textbf{\textsf{$title$}}} + $if(subtitle)$ + \vskip 1em + {\Large \textsf{$subtitle$}} + $endif$ + \vskip 2em + \noindent {\Large \textsf{$for(author)$$author$$sep$, $endfor$}} + \vfill +} +$endif$ + + +$if(titlepage-background)$ +$else$ +\textsf{$date$} +$endif$ +\end{flushleft} +\end{titlepage} +\restoregeometry +$endif$ +$endif$ + +%% +%% end titlepage +%% + +$if(has-frontmatter)$ +\frontmatter +$endif$ +$if(title)$ +$if(beamer)$ +\frame{\titlepage} +$endif$ +$if(abstract)$ +\begin{abstract} +$abstract$ +\end{abstract} +$endif$ +$endif$ + +$if(first-chapter)$ +\setcounter{chapter}{$first-chapter$} +\addtocounter{chapter}{-1} +$endif$ + +$for(include-before)$ +$include-before$ + +$endfor$ +$if(toc)$ +$if(toc-title)$ +\renewcommand*\contentsname{$toc-title$} +$endif$ +$if(beamer)$ +\begin{frame} +$if(toc-title)$ + \frametitle{$toc-title$} +$endif$ + \tableofcontents[hideallsubsections] +\end{frame} +$if(toc-own-page)$ +\newpage +$endif$ +$else$ +{ +$if(colorlinks)$ +\hypersetup{linkcolor=$if(toccolor)$$toccolor$$else$$endif$} +$endif$ +\setcounter{tocdepth}{$if(toc-depth)$$toc-depth$$else$3$endif$} +\tableofcontents +$if(toc-own-page)$ +\newpage +$endif$ +} +$endif$ +$endif$ +$if(lot)$ +\listoftables +\newpage +$endif$ +$if(lof)$ +\listoffigures +\newpage +$endif$ +$if(linestretch)$ +\setstretch{$linestretch$} +$endif$ +$if(has-frontmatter)$ +\mainmatter +$endif$ +$body$ + +$if(has-frontmatter)$ +\backmatter +$endif$ +$if(natbib)$ +$if(bibliography)$ +$if(biblio-title)$ +$if(has-chapters)$ +\renewcommand\bibname{$biblio-title$} +$else$ +\renewcommand\refname{$biblio-title$} +$endif$ +$endif$ +$if(beamer)$ +\begin{frame}[allowframebreaks]{$biblio-title$} + \bibliographytrue +$endif$ + \bibliography{$for(bibliography)$$bibliography$$sep$,$endfor$} +$if(beamer)$ +\end{frame} +$endif$ + +$endif$ +$endif$ +$if(biblatex)$ +$if(beamer)$ +\begin{frame}[allowframebreaks]{$biblio-title$} + \bibliographytrue + \printbibliography[heading=none] +\end{frame} +$else$ +\printbibliography$if(biblio-title)$[title=$biblio-title$]$endif$ +$endif$ + +$endif$ +$for(include-after)$ +$include-after$ + +$endfor$ +\end{document} diff --git a/doc/vec.conf b/doc/vec.conf new file mode 100644 index 0000000..856e7eb --- /dev/null +++ b/doc/vec.conf @@ -0,0 +1,243 @@ + + +############################################################################# +# Parser keywords +############################################################################# +# Polarity +HIGHActiveSuffix=_pi +LOWActiveSuffix=_ni + +# Special ports +#resetName=rst_n +#clockName=clk +resetName=rst_ni +clockName=clk_i +#resetName=rst_pi +#clockName=clk_i +#resetName=rst_i +#clockName=clk_i +#clockName=CLOCK_50 +#resetName=KEY +#resetName=reset +#clockName=clock + +# Default label to print above entity box. Leave empty if no label is desired +default_label= + + +############################################################################# +# Font settings +############################################################################# +# Label +label.fontFamily=Arial +label.fontSize=10pt +label.fontWeight=normal + +# Entity +entity.fontFamily=Arial +entity.fontSize=12pt +entity.fontWeight=bold + +#Port +port.fontFamily=Arial +port.fontSize=12pt +port.fontWeight=normal + +# Generic signal +genericSignal.fontFamily=Arial +genericSignal.fontSize=10pt +genericSignal.fontWeight=normal + +# Vector +vector.fontFamily=Arial +vector.fontSize=10pt +vector.fontWeight=normal + + +############################################################################# +# Shape settings +############################################################################# +# Margin +vertical_Margin=0.5 +horizontal_Margin=0.5 +fixed_Width=0 + +# Label +label.stroke=none +label.strokeWidth=0.00cm +label.strokeColor=#000000 +label.fill=none +label.fillColor=#FFFFFF + +# Entity +entity.stroke=solid +entity.strokeWidth=0.05cm +entity.strokeColor=#000000 +entity.fill=solid +entity.fillColor=#FFFFFF + +# Port +port.stroke=none +port.strokeWidth=0.00cm +port.strokeColor=#FFF +port.fill=none +port.fillColor=#FFFFFF + +# Connector +connector.stroke=solid +connector.strokeWidth=0.025cm +connector.strokeColor=#000000 +connector.fill=solid +connector.fillColor=#FFFFFF + +# Generics +generics.stroke=solid +generics.strokeWidth=0.02cm +generics.strokeColor=#BFBFBF +generics.fill=solid +generics.fillColor=#F2F2F2 + +# Generic signal +genericSignal.stroke=none +genericSignal.strokeWidth=0.00cm +genericSignal.strokeColor=#C2C2C2 +genericSignal.fill=none +genericSignal.fillColor=#FFFFFF + + +############################################################################# +# Doku Wiki markup settings +############################################################################# +DokuWiki.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located. +# Both absolute and relative path are working +DokuWiki.outputPath=dokuwiki + + +############################################################################# +# Markdown settings +############################################################################# +Markdown.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located. +# Both absolute and relative path are working +Markdown.outputPath=markdown + + +############################################################################# +# LaTeX settings +############################################################################# +LaTeX.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located. +# Both absolute and relative path are working +LaTeX.outputPath=latex + +# VEC can add a 'table' environment to label and place the actual tabular element. +# VEC will use the entity name as caption and label +LaTeX.addTable=1 +LaTeX.centering=1 +LaTeX.caption=1 +LaTeX.label=1 + + +############################################################################# +# Table export settings +############################################################################# +# Set the entity information the table should contain +Table.exportType=1 +Table.exportDirection=1 +Table.exportPolarity=1 +Table.exportDescription=1 +Table.exportBlank1=0 +Table.exportBlank2=0 + +# Export generics. Generate a seperate table for generic signals +Table.exportGenerics=1 + +# Heading formatting +Table.boldHeadings=1 + +# Column alignments +Table.centeredName=0 +Table.centeredType=0 +Table.centeredDirection=1 +Table.centeredPolarity=1 +Table.centeredDescription=0 +Table.centeredBlank=0 +Table.centeredGenericName=0 +Table.centeredGenericType=0 +Table.centeredGenericDefaultValue=0 + +# Column headings +Table.Name_heading=Name +Table.Type_heading=Type +Table.Direction_heading=Direction +Table.Polarity_heading=Polarity +Table.Description_heading=Description +Table.Blank1_heading=Blank1 +Table.Blank2_heading=Blank2 +Table.GenericName=Name +Table.GenericType=Type +Table.GenericDefaultValue=Default value + +# Captions for the port directions +Table.caption_IN=IN +Table.caption_OUT=OUT +Table.caption_INOUT=INOUT +Table.caption_BUFFER=BUFFER +Table.caption_LINKAGE=LINKAGE + +# Polarity labels +Table.caption_HIGHactive=HIGH +Table.caption_LOWactive=LOW + +# Vector settings +Table.combineNameAndType=0 +Table.showArrayLength=1 +Table.arrayNotation=1 + + +############################################################################# +# PATH settings +############################################################################# +# Path to LibreOffice executable. +# e.g. for WINDOWS +# C:\Program Files (x86)\LibreOffice 4.0\program\soffice.exe +# e.g. for UNIX platforms +# /usr/bin/soffice + +#PATH.soffice=C:\Program Files (x86)\LibreOffice 3.6\program\soffice.exe +PATH.soffice=/usr/bin/soffice + + +############################################################################# +# FODG Export +############################################################################# +FODG.enableExport=1 + +# If left empty the output files will be placed in the same directory where the executable is located +#FODG.outputPath=fodg +FODG.outputPath=. + + +############################################################################# +# PNG Export +############################################################################# +PNG.enableExport=1 + +# If left empty the output files will be placed in the same directory where the executable is located +#PNG.outputPath=png +PNG.outputPath=. + + +############################################################################# +# SVG Export +############################################################################# +SVG.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located +#SVG.outputPath=svg +SVG.outputPath=. + diff --git a/matlab/audio/audio_first.slx b/matlab/audio/audio_first.slx Binary files differnew file mode 100644 index 0000000..848e1be --- /dev/null +++ b/matlab/audio/audio_first.slx diff --git a/matlab/audio/audio_tone.slx b/matlab/audio/audio_tone.slx Binary files differnew file mode 100644 index 0000000..5b8586b --- /dev/null +++ b/matlab/audio/audio_tone.slx diff --git a/matlab/audio/makefile b/matlab/audio/makefile new file mode 100644 index 0000000..37ef569 --- /dev/null +++ b/matlab/audio/makefile @@ -0,0 +1,4 @@ +PROJECT=audio_first +TOPLEVEL=$(PROJECT)/ml_audio + +include ../makefile diff --git a/matlab/makefile b/matlab/makefile new file mode 100644 index 0000000..2832597 --- /dev/null +++ b/matlab/makefile @@ -0,0 +1,15 @@ +################################################################### +# Main Targets +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make hdl" - create vhdl files from matlab simulink model' + @echo ' "make clean" - to remove all generated files' + +hdl: $(PROJECT).slx + # create hdl from matlab + matlab -nodisplay -nosplash -nodesktop -r "$(PROJECT); makehdl('$(TOPLEVEL)') ;exit;" + +clean: + rm -rf hdl_prj slprj *~ diff --git a/pnr/de1_and2gate/de1_and2gate_pins.tcl b/pnr/de1_and2gate/de1_and2gate_pins.tcl new file mode 100644 index 0000000..9c70aec --- /dev/null +++ b/pnr/de1_and2gate/de1_and2gate_pins.tcl @@ -0,0 +1,10 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_and2gate/makefile b/pnr/de1_and2gate/makefile new file mode 100644 index 0000000..103b8c1 --- /dev/null +++ b/pnr/de1_and2gate/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = and2gate +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_audio/de1_audio_pins.tcl b/pnr/de1_audio/de1_audio_pins.tcl new file mode 100644 index 0000000..28fe709 --- /dev/null +++ b/pnr/de1_audio/de1_audio_pins.tcl @@ -0,0 +1,23 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] + + diff --git a/pnr/de1_audio/makefile b/pnr/de1_audio/makefile new file mode 100644 index 0000000..0a8636c --- /dev/null +++ b/pnr/de1_audio/makefile @@ -0,0 +1,16 @@ +SIM_PROJECT_NAME = de1_audio +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile + + diff --git a/pnr/de1_binto7segment/de1_binto7segment_pins.tcl b/pnr/de1_binto7segment/de1_binto7segment_pins.tcl new file mode 100644 index 0000000..ad20fb6 --- /dev/null +++ b/pnr/de1_binto7segment/de1_binto7segment_pins.tcl @@ -0,0 +1,20 @@ +# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+# ----------------------------------------------------------------------------
diff --git a/pnr/de1_binto7segment/makefile b/pnr/de1_binto7segment/makefile new file mode 100644 index 0000000..60faed4 --- /dev/null +++ b/pnr/de1_binto7segment/makefile @@ -0,0 +1,53 @@ +## ----------------------------------------------------------------------------
+## Script : makefile
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber, Friedrich Beckmann
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+## it is based on a design directory structure described in
+## ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration:
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite:
+# - mandatory design directory structure (see end of file)
+# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = binto7segment
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+# DE1
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+# DEMMK
+# FAMILY = "MAX II"
+# DEVICE = EPM2210F324C3
+# PROGFILEEXT = pof
+# DE2
+#FAMILY = "Cyclone II"
+#DEVICE = EP2C35F484C7
+#PROGFILEEXT = sof
+# DE0
+#FAMILY = "Cyclone IV E"
+#DEVICE = EP4CE22F17C6
+#PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined.
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+
diff --git a/pnr/de1_cntdn/de1_cntdn_pins.tcl b/pnr/de1_cntdn/de1_cntdn_pins.tcl new file mode 100644 index 0000000..cb02476 --- /dev/null +++ b/pnr/de1_cntdn/de1_cntdn_pins.tcl @@ -0,0 +1,14 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +set_location_assignment PIN_E15 -to GPO_1[5] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_cntdn/makefile b/pnr/de1_cntdn/makefile new file mode 100644 index 0000000..fc13333 --- /dev/null +++ b/pnr/de1_cntdn/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = cntdn +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl b/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl new file mode 100644 index 0000000..81d32b6 --- /dev/null +++ b/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl @@ -0,0 +1,16 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +set_location_assignment PIN_E15 -to GPO_1[5] +set_location_assignment PIN_F15 -to GPO_1[6] +set_location_assignment PIN_G16 -to GPO_1[7] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_cntdnmodm/makefile b/pnr/de1_cntdnmodm/makefile new file mode 100644 index 0000000..72e14e0 --- /dev/null +++ b/pnr/de1_cntdnmodm/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = cntdnmodm +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_incrementer/de1_incrementer_pins.tcl b/pnr/de1_incrementer/de1_incrementer_pins.tcl new file mode 100644 index 0000000..7f21d8a --- /dev/null +++ b/pnr/de1_incrementer/de1_incrementer_pins.tcl @@ -0,0 +1,25 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY +set_location_assignment PIN_H12 -to GPI_1[0] +set_location_assignment PIN_H13 -to GPI_1[1] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_incrementer/makefile b/pnr/de1_incrementer/makefile new file mode 100644 index 0000000..2202ce2 --- /dev/null +++ b/pnr/de1_incrementer/makefile @@ -0,0 +1,55 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = incrementer +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/binto7segment_truthtable.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_mux2to1/de1_mux2to1_pins.tcl b/pnr/de1_mux2to1/de1_mux2to1_pins.tcl new file mode 100644 index 0000000..d6984a3 --- /dev/null +++ b/pnr/de1_mux2to1/de1_mux2to1_pins.tcl @@ -0,0 +1,9 @@ +# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_R20 -to LEDR
+# ----------------------------------------------------------------------------
diff --git a/pnr/de1_mux2to1/makefile b/pnr/de1_mux2to1/makefile new file mode 100644 index 0000000..b4c830b --- /dev/null +++ b/pnr/de1_mux2to1/makefile @@ -0,0 +1,87 @@ +## ----------------------------------------------------------------------------
+## Script : makefile
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber, Friedrich Beckmann
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+## it is based on a design directory structure described in
+## ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration:
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite:
+# - mandatory design directory structure (see end of file)
+# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = mux2to1
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+# DE1
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+# DEMMK
+# FAMILY = "MAX II"
+# DEVICE = EPM2210F324C3
+# PROGFILEEXT = pof
+# DE2
+#FAMILY = "Cyclone II"
+#DEVICE = EP2C35F484C7
+#PROGFILEEXT = sof
+# DE0
+#FAMILY = "Cyclone IV E"
+#DEVICE = EP4CE22F17C6
+#PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined.
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description:
+## ------------
+## assumes the following design directory structure as prerequisite
+##
+## DigitaltechnikPraktikum
+## |
+## +---src
+## | and2gate_equation.vhd
+## | invgate_equation.vhd
+## | mux2to1_structure.vhd
+## | or2gate_equation.vhd
+## | t_mux2to1.vhd
+## | de1_mux2to1_structure.vhd
+## |
+## +---sim
+## | | makefile
+## | |
+## | \---mux2to1
+## | makefile
+## | makefile.sources
+## |
+## +---pnr
+## | | makefile
+## | |
+## | \---de1_mux2to1
+## | de1_mux2to1_pins.tcl
+## | makefile
+## |
+## \---scripts
+## de1_pin_assignments_minimumio.csv
+## de1_pin_assignments_minimumio.tcl
+## modelsim.ini
+## quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
diff --git a/pnr/de1_pwm/de1_pwm_pins.tcl b/pnr/de1_pwm/de1_pwm_pins.tcl new file mode 100644 index 0000000..1d79959 --- /dev/null +++ b/pnr/de1_pwm/de1_pwm_pins.tcl @@ -0,0 +1,27 @@ +# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_H14 -to GPO_1[2]
+# ----------------------------------------------------------------------------
diff --git a/pnr/de1_pwm/makefile b/pnr/de1_pwm/makefile new file mode 100644 index 0000000..5ed5024 --- /dev/null +++ b/pnr/de1_pwm/makefile @@ -0,0 +1,87 @@ +## ----------------------------------------------------------------------------
+## Script : makefile
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber, Friedrich Beckmann
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+## it is based on a design directory structure described in
+## ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration:
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite:
+# - mandatory design directory structure (see end of file)
+# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = pwm
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+# DE1
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+# DEMMK
+# FAMILY = "MAX II"
+# DEVICE = EPM2210F324C3
+# PROGFILEEXT = pof
+# DE2
+#FAMILY = "Cyclone II"
+#DEVICE = EP2C35F484C7
+#PROGFILEEXT = sof
+# DE0
+#FAMILY = "Cyclone IV E"
+#DEVICE = EP4CE22F17C6
+#PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined.
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description:
+## ------------
+## assumes the following design directory structure as prerequisite
+##
+## DigitaltechnikPraktikum
+## |
+## +---src
+## | and2gate_equation.vhd
+## | invgate_equation.vhd
+## | mux2to1_structure.vhd
+## | or2gate_equation.vhd
+## | t_mux2to1.vhd
+## | de1_mux2to1_structure.vhd
+## |
+## +---sim
+## | | makefile
+## | |
+## | \---mux2to1
+## | makefile
+## | makefile.sources
+## |
+## +---pnr
+## | | makefile
+## | |
+## | \---de1_mux2to1
+## | de1_mux2to1_pins.tcl
+## | makefile
+## |
+## \---scripts
+## de1_pin_assignments_minimumio.csv
+## de1_pin_assignments_minimumio.tcl
+## modelsim.ini
+## quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
diff --git a/pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl b/pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl new file mode 100644 index 0000000..8eba56a --- /dev/null +++ b/pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl @@ -0,0 +1,36 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY +set_location_assignment PIN_H12 -to GPI_1[0] +set_location_assignment PIN_H13 -to GPI_1[1] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_pwm_incrementer/makefile b/pnr/de1_pwm_incrementer/makefile new file mode 100644 index 0000000..c894956 --- /dev/null +++ b/pnr/de1_pwm_incrementer/makefile @@ -0,0 +1,55 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = pwm_incrementer +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/binto7segment_truthtable.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_tone/de1_tone_pins.tcl b/pnr/de1_tone/de1_tone_pins.tcl new file mode 100644 index 0000000..e9c32ae --- /dev/null +++ b/pnr/de1_tone/de1_tone_pins.tcl @@ -0,0 +1,33 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] + + diff --git a/pnr/de1_tone/makefile b/pnr/de1_tone/makefile new file mode 100644 index 0000000..e9cf6e6 --- /dev/null +++ b/pnr/de1_tone/makefile @@ -0,0 +1,14 @@ +SIM_PROJECT_NAME = de1_tone +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile diff --git a/pnr/makefile b/pnr/makefile new file mode 100644 index 0000000..ffc1cf0 --- /dev/null +++ b/pnr/makefile @@ -0,0 +1,92 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure shown at +## the end of this file. +## ---------------------------------------------------------------------------- + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make qproject" to create quartus project only' + @echo ' "make compile" to synthesize the design' + @echo ' "make prog" to configure programmable device' + @echo ' "make quartus" to start quartus graphical user interface' + @echo ' "make clean" to remove all generated files' + +qproject: $(PROJECT).qpf + +$(PROJECT).sdc: + # create a default timing constraint file assuming CLOCK_50 + echo "create_clock -period 20.000 -name CLOCK_50 [get_ports CLOCK_50]" > $(PROJECT).sdc + echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc + echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc + +$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl $(PROJECT).sdc + # assign VHDL design files + rm -rf quartus_vhdl_source_files.tcl + for source_file in $(SOURCE_FILES); do \ + echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \ + done + # just create a quartus project + quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT) -family $(FAMILY) -device $(DEVICE) + +compile: $(PROJECT).qpf flowsummary.log + +flowsummary.log: $(SOURCE_FILES) + quartus_sh -t ../../scripts/quartus_project_flow.tcl -projectname $(PROJECT) -process compile + +prog: $(PROJECT).qpf flowsummary.log + quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).$(PROGFILEEXT)" + +quartus: $(PROJECT).qpf + # start quartus gui + quartus $(PROJECT).qpf & + +clean: + rm -rf *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).* *~ + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/scripts/create_quartus_project_settings.tcl b/scripts/create_quartus_project_settings.tcl new file mode 100644 index 0000000..ab55593 --- /dev/null +++ b/scripts/create_quartus_project_settings.tcl @@ -0,0 +1,84 @@ +## ---------------------------------------------------------------------------- +## Script : create_quartus_project_settings.tcl +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, F. Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: create a quartus project with default settings for device, +## unused pins, ... +## expects project name as command line parameter +## e.g. +## quartus_sh -t create_quartus_project_settings.tcl -projectname de1_mux2to1 +## -family "Cyclone II" -device EP2C20F484C7 +## ---------------------------------------------------------------------------- +## Revisions : see end of file +## ---------------------------------------------------------------------------- + +package require cmdline +# Load Quartus II Tcl Project package +package require ::quartus::project + +# ---------------------------------------------------------------------------- +# Declare command line parameters +# ---------------------------------------------------------------------------- +set parameters { + {projectname.arg "" "Project Name"} + {family.arg "" "FPGA Family"} + {device.arg "" "FPGA Device"} +} +array set arg [::cmdline::getoptions argv $parameters] + +# ---------------------------------------------------------------------------- +# Verify required paramters +# ---------------------------------------------------------------------------- +set requiredParameters {projectname family device} +foreach parameter $requiredParameters { + if {$arg($parameter) == ""} { + puts stderr "Missing required parameter: -$parameter" + exit 1 + } +} + + + # ---------------------------------------------------------------------------- + # Create project + # ---------------------------------------------------------------------------- + project_new $arg(projectname) -overwrite + + # ---------------------------------------------------------------------------- + # Assign family, device, and top-level file + # ---------------------------------------------------------------------------- + set_global_assignment -name FAMILY $arg(family) + set_global_assignment -name DEVICE $arg(device) + + # ---------------------------------------------------------------------------- + # Default settings + # ---------------------------------------------------------------------------- + set_global_assignment -name USE_CONFIGURATION_DEVICE ON + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 + + # ---------------------------------------------------------------------------- + # Design files + # ---------------------------------------------------------------------------- + #set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd + #set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd + source quartus_vhdl_source_files.tcl + + # ---------------------------------------------------------------------------- + # Pin Assignments + # ---------------------------------------------------------------------------- + # set_location_assignment PIN_L1 -to CLOCK_50 + source $arg(projectname)_pins.tcl + + # ---------------------------------------------------------------------------- + # Close project + # ---------------------------------------------------------------------------- + project_close + + +## ---------------------------------------------------------------------------- +## Revisions: +## ---------- +## $Id:$ +## ---------------------------------------------------------------------------- diff --git a/scripts/de1_pin_assignments_minimumio.tcl b/scripts/de1_pin_assignments_minimumio.tcl new file mode 100644 index 0000000..d9d3470 --- /dev/null +++ b/scripts/de1_pin_assignments_minimumio.tcl @@ -0,0 +1,282 @@ +set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_location_assignment PIN_A13 -to GPI_0[0]
+set_location_assignment PIN_B13 -to GPI_0[1]
+set_location_assignment PIN_A14 -to GPI_0[2]
+set_location_assignment PIN_B14 -to GPI_0[3]
+set_location_assignment PIN_A15 -to GPI_0[4]
+set_location_assignment PIN_B15 -to GPI_0[5]
+set_location_assignment PIN_A16 -to GPI_0[6]
+set_location_assignment PIN_B16 -to GPI_0[7]
+set_location_assignment PIN_A17 -to GPI_0[8]
+set_location_assignment PIN_B17 -to GPI_0[9]
+set_location_assignment PIN_A18 -to GPI_0[10]
+set_location_assignment PIN_B18 -to GPI_0[11]
+set_location_assignment PIN_A19 -to GPI_0[12]
+set_location_assignment PIN_B19 -to GPI_0[13]
+set_location_assignment PIN_A20 -to GPI_0[14]
+set_location_assignment PIN_B20 -to GPI_0[15]
+set_location_assignment PIN_C21 -to GPI_0[16]
+set_location_assignment PIN_C22 -to GPI_0[17]
+set_location_assignment PIN_D21 -to GPI_0[18]
+set_location_assignment PIN_D22 -to GPI_0[19]
+set_location_assignment PIN_E21 -to GPI_0[20]
+set_location_assignment PIN_E22 -to GPI_0[21]
+set_location_assignment PIN_F21 -to GPI_0[22]
+set_location_assignment PIN_F22 -to GPI_0[23]
+set_location_assignment PIN_G21 -to GPI_0[24]
+set_location_assignment PIN_G22 -to GPI_0[25]
+set_location_assignment PIN_J21 -to GPI_0[26]
+set_location_assignment PIN_J22 -to GPI_0[27]
+set_location_assignment PIN_K21 -to GPI_0[28]
+set_location_assignment PIN_K22 -to GPI_0[29]
+set_location_assignment PIN_J19 -to GPI_0[30]
+set_location_assignment PIN_J20 -to GPI_0[31]
+set_location_assignment PIN_J18 -to GPI_0[32]
+set_location_assignment PIN_K20 -to GPI_0[33]
+set_location_assignment PIN_L19 -to GPI_0[34]
+set_location_assignment PIN_L18 -to GPI_0[35]
+set_location_assignment PIN_H12 -to GPI_1[0]
+set_location_assignment PIN_H13 -to GPI_1[1]
+set_location_assignment PIN_H14 -to GPI_1[2]
+set_location_assignment PIN_G15 -to GPI_1[3]
+set_location_assignment PIN_E14 -to GPI_1[4]
+set_location_assignment PIN_E15 -to GPI_1[5]
+set_location_assignment PIN_F15 -to GPI_1[6]
+set_location_assignment PIN_G16 -to GPI_1[7]
+set_location_assignment PIN_F12 -to GPI_1[8]
+set_location_assignment PIN_F13 -to GPI_1[9]
+set_location_assignment PIN_C14 -to GPI_1[10]
+set_location_assignment PIN_D14 -to GPI_1[11]
+set_location_assignment PIN_D15 -to GPI_1[12]
+set_location_assignment PIN_D16 -to GPI_1[13]
+set_location_assignment PIN_C17 -to GPI_1[14]
+set_location_assignment PIN_C18 -to GPI_1[15]
+set_location_assignment PIN_C19 -to GPI_1[16]
+set_location_assignment PIN_C20 -to GPI_1[17]
+set_location_assignment PIN_D19 -to GPI_1[18]
+set_location_assignment PIN_D20 -to GPI_1[19]
+set_location_assignment PIN_E20 -to GPI_1[20]
+set_location_assignment PIN_F20 -to GPI_1[21]
+set_location_assignment PIN_E19 -to GPI_1[22]
+set_location_assignment PIN_E18 -to GPI_1[23]
+set_location_assignment PIN_G20 -to GPI_1[24]
+set_location_assignment PIN_G18 -to GPI_1[25]
+set_location_assignment PIN_G17 -to GPI_1[26]
+set_location_assignment PIN_H17 -to GPI_1[27]
+set_location_assignment PIN_J15 -to GPI_1[28]
+set_location_assignment PIN_H18 -to GPI_1[29]
+set_location_assignment PIN_N22 -to GPI_1[30]
+set_location_assignment PIN_N21 -to GPI_1[31]
+set_location_assignment PIN_P15 -to GPI_1[32]
+set_location_assignment PIN_N15 -to GPI_1[33]
+set_location_assignment PIN_P17 -to GPI_1[34]
+set_location_assignment PIN_P18 -to GPI_1[35]
+set_location_assignment PIN_A13 -to GPO_0[0]
+set_location_assignment PIN_B13 -to GPO_0[1]
+set_location_assignment PIN_A14 -to GPO_0[2]
+set_location_assignment PIN_B14 -to GPO_0[3]
+set_location_assignment PIN_A15 -to GPO_0[4]
+set_location_assignment PIN_B15 -to GPO_0[5]
+set_location_assignment PIN_A16 -to GPO_0[6]
+set_location_assignment PIN_B16 -to GPO_0[7]
+set_location_assignment PIN_A17 -to GPO_0[8]
+set_location_assignment PIN_B17 -to GPO_0[9]
+set_location_assignment PIN_A18 -to GPO_0[10]
+set_location_assignment PIN_B18 -to GPO_0[11]
+set_location_assignment PIN_A19 -to GPO_0[12]
+set_location_assignment PIN_B19 -to GPO_0[13]
+set_location_assignment PIN_A20 -to GPO_0[14]
+set_location_assignment PIN_B20 -to GPO_0[15]
+set_location_assignment PIN_C21 -to GPO_0[16]
+set_location_assignment PIN_C22 -to GPO_0[17]
+set_location_assignment PIN_D21 -to GPO_0[18]
+set_location_assignment PIN_D22 -to GPO_0[19]
+set_location_assignment PIN_E21 -to GPO_0[20]
+set_location_assignment PIN_E22 -to GPO_0[21]
+set_location_assignment PIN_F21 -to GPO_0[22]
+set_location_assignment PIN_F22 -to GPO_0[23]
+set_location_assignment PIN_G21 -to GPO_0[24]
+set_location_assignment PIN_G22 -to GPO_0[25]
+set_location_assignment PIN_J21 -to GPO_0[26]
+set_location_assignment PIN_J22 -to GPO_0[27]
+set_location_assignment PIN_K21 -to GPO_0[28]
+set_location_assignment PIN_K22 -to GPO_0[29]
+set_location_assignment PIN_J19 -to GPO_0[30]
+set_location_assignment PIN_J20 -to GPO_0[31]
+set_location_assignment PIN_J18 -to GPO_0[32]
+set_location_assignment PIN_K20 -to GPO_0[33]
+set_location_assignment PIN_L19 -to GPO_0[34]
+set_location_assignment PIN_L18 -to GPO_0[35]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_H14 -to GPO_1[2]
+set_location_assignment PIN_G15 -to GPO_1[3]
+set_location_assignment PIN_E14 -to GPO_1[4]
+set_location_assignment PIN_E15 -to GPO_1[5]
+set_location_assignment PIN_F15 -to GPO_1[6]
+set_location_assignment PIN_G16 -to GPO_1[7]
+set_location_assignment PIN_F12 -to GPO_1[8]
+set_location_assignment PIN_F13 -to GPO_1[9]
+set_location_assignment PIN_C14 -to GPO_1[10]
+set_location_assignment PIN_D14 -to GPO_1[11]
+set_location_assignment PIN_D15 -to GPO_1[12]
+set_location_assignment PIN_D16 -to GPO_1[13]
+set_location_assignment PIN_C17 -to GPO_1[14]
+set_location_assignment PIN_C18 -to GPO_1[15]
+set_location_assignment PIN_C19 -to GPO_1[16]
+set_location_assignment PIN_C20 -to GPO_1[17]
+set_location_assignment PIN_D19 -to GPO_1[18]
+set_location_assignment PIN_D20 -to GPO_1[19]
+set_location_assignment PIN_E20 -to GPO_1[20]
+set_location_assignment PIN_F20 -to GPO_1[21]
+set_location_assignment PIN_E19 -to GPO_1[22]
+set_location_assignment PIN_E18 -to GPO_1[23]
+set_location_assignment PIN_G20 -to GPO_1[24]
+set_location_assignment PIN_G18 -to GPO_1[25]
+set_location_assignment PIN_G17 -to GPO_1[26]
+set_location_assignment PIN_H17 -to GPO_1[27]
+set_location_assignment PIN_J15 -to GPO_1[28]
+set_location_assignment PIN_H18 -to GPO_1[29]
+set_location_assignment PIN_N22 -to GPO_1[30]
+set_location_assignment PIN_N21 -to GPO_1[31]
+set_location_assignment PIN_P15 -to GPO_1[32]
+set_location_assignment PIN_N15 -to GPO_1[33]
+set_location_assignment PIN_P17 -to GPO_1[34]
+set_location_assignment PIN_P18 -to GPO_1[35]
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
\ No newline at end of file diff --git a/scripts/modelsim.ini b/scripts/modelsim.ini new file mode 100644 index 0000000..d3412fe --- /dev/null +++ b/scripts/modelsim.ini @@ -0,0 +1,351 @@ +;; ----------------------------------------------------------------------------
+;; Script : modelsim.ini
+;; ----------------------------------------------------------------------------
+;; Author : Johann Faerber
+;; Company : University of Applied Sciences Augsburg
+;; ----------------------------------------------------------------------------
+;; Description: original version modified
+;; - deleted all VHDL and Verilog device libraries
+;; - modified compiler standard to VHDL93 = 2008
+;; ----------------------------------------------------------------------------
+;; Revisions : see end of file
+;; ----------------------------------------------------------------------------
+
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2008
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer). The other settings
+; are to send messages only to the transcript or only to the
+; wlf file. The valid values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+
+;; ----------------------------------------------------------------------------
+;; Revisions:
+;; ----------
+;; $Id:$
+;; ----------------------------------------------------------------------------
diff --git a/scripts/quartus_project_flow.tcl b/scripts/quartus_project_flow.tcl new file mode 100644 index 0000000..2894685 --- /dev/null +++ b/scripts/quartus_project_flow.tcl @@ -0,0 +1,84 @@ +## ---------------------------------------------------------------------------- +## Script : quartus_project_flow.tcl +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, F. Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: executes process steps in a quartus project +## depending on the parameter process +## expects project name as command line parameter +## e.g. +## quartus_sh -t quartus_project_flow.tcl -projectname de1_mux2to1 +## -process compile +## ---------------------------------------------------------------------------- +## Revisions : see end of file +## ---------------------------------------------------------------------------- + +package require cmdline +# Load Quartus II Tcl Project package +package require ::quartus::project + +# ---------------------------------------------------------------------------- +# Declare command line parameters +# ---------------------------------------------------------------------------- +set parameters { + {projectname.arg "" "Project Name"} + {process.arg "" "Process Step"} +} +array set arg [::cmdline::getoptions argv $parameters] + +# ---------------------------------------------------------------------------- +# Verify required paramters +# ---------------------------------------------------------------------------- +set requiredParameters {projectname process} +foreach parameter $requiredParameters { + if {$arg($parameter) == ""} { + puts stderr "Missing required parameter: -$parameter" + exit 1 + } +} + +# ---------------------------------------------------------------------------- +# Check, if project exists +# ---------------------------------------------------------------------------- +if { ![project_exists $arg(projectname)] } { + post_message -type error "Project $arg(projectname) does not exist" + exit +} + # ---------------------------------------------------------------------------- + # Open project + # ---------------------------------------------------------------------------- + project_open $arg(projectname) + + # ---------------------------------------------------------------------------- + # Run specified design flow by parameter -process + # ---------------------------------------------------------------------------- + load_package flow + + if { $arg(process) == "compile" } { + execute_flow -compile + } elseif { $arg(process) == "analysis_and_elaboration" } { + execute_flow -analysis_and_elaboration + } else { + post_message -type error "Process step $arg(process) not allowed !" + exit + } + + # ---------------------------------------------------------------------------- + # Write Reports + # ---------------------------------------------------------------------------- + load_package report + load_report $arg(projectname) + write_report_panel -file flowsummary.log "Flow Summary" + + # ---------------------------------------------------------------------------- + # Close project + # ---------------------------------------------------------------------------- + project_close + + +## ---------------------------------------------------------------------------- +## Revisions: +## ---------- +## $Id:$ +## ---------------------------------------------------------------------------- diff --git a/sim/and2gate/makefile b/sim/and2gate/makefile new file mode 100644 index 0000000..e523dc3 --- /dev/null +++ b/sim/and2gate/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = and2gate + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/and2gate/makefile.sources b/sim/and2gate/makefile.sources new file mode 100644 index 0000000..cac390c --- /dev/null +++ b/sim/and2gate/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/cntdn/makefile b/sim/cntdn/makefile new file mode 100644 index 0000000..1be2176 --- /dev/null +++ b/sim/cntdn/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = cntdn + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/cntdn/makefile.sources b/sim/cntdn/makefile.sources new file mode 100644 index 0000000..af4874d --- /dev/null +++ b/sim/cntdn/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/cntdn_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/cntdnmodm/makefile b/sim/cntdnmodm/makefile new file mode 100644 index 0000000..060a0ad --- /dev/null +++ b/sim/cntdnmodm/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = cntdnmodm + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/cntdnmodm/makefile.sources b/sim/cntdnmodm/makefile.sources new file mode 100644 index 0000000..4752d19 --- /dev/null +++ b/sim/cntdnmodm/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/cntdnmodm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/de1_audio/makefile b/sim/de1_audio/makefile new file mode 100644 index 0000000..99b022e --- /dev/null +++ b/sim/de1_audio/makefile @@ -0,0 +1,10 @@ +PROJECT = de1_audio + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + diff --git a/sim/de1_audio/makefile.sources b/sim/de1_audio/makefile.sources new file mode 100644 index 0000000..ee901cc --- /dev/null +++ b/sim/de1_audio/makefile.sources @@ -0,0 +1,14 @@ +SYN_SOURCE_FILES = \ +../../src/adcintf.vhd \ +../../src/bclk.vhd \ +../../src/dacintf.vhd \ +../../src/fsgen.vhd \ +../../src/i2c_sub.vhd \ +../../src/i2c.vhd \ +../../src/i2c_write.vhd \ +../../src/mclk.vhd \ +../../src/memory.vhd \ +../../src/ringbuf.vhd \ +../../src/audio.vhd \ +../../src/de1_audio.vhd + diff --git a/sim/de1_tone/makefile b/sim/de1_tone/makefile new file mode 100644 index 0000000..7eb97d3 --- /dev/null +++ b/sim/de1_tone/makefile @@ -0,0 +1,9 @@ +PROJECT = de1_tone + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile diff --git a/sim/de1_tone/makefile.sources b/sim/de1_tone/makefile.sources new file mode 100644 index 0000000..46993a5 --- /dev/null +++ b/sim/de1_tone/makefile.sources @@ -0,0 +1,13 @@ +SYN_SOURCE_FILES = \ +../../src/adcintf.vhd \ +../../src/bclk.vhd \ +../../src/dacintf.vhd \ +../../src/fsgen.vhd \ +../../src/i2c_sub.vhd \ +../../src/i2c.vhd \ +../../src/i2c_write.vhd \ +../../src/mclk.vhd \ +../../src/audio.vhd \ +../../src/tone_rtl.vhd \ +../../src/de1_tone.vhd + diff --git a/sim/falling_edge_detector/makefile b/sim/falling_edge_detector/makefile new file mode 100644 index 0000000..48792e4 --- /dev/null +++ b/sim/falling_edge_detector/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = falling_edge_detector + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/falling_edge_detector/makefile.sources b/sim/falling_edge_detector/makefile.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_qfsm.sources b/sim/falling_edge_detector/makefile_qfsm.sources new file mode 100644 index 0000000..5b3eeec --- /dev/null +++ b/sim/falling_edge_detector/makefile_qfsm.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/falling_edge_detector_qfsm.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_rtl.sources b/sim/falling_edge_detector/makefile_rtl.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile_rtl.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_structure.sources b/sim/falling_edge_detector/makefile_structure.sources new file mode 100644 index 0000000..f644c26 --- /dev/null +++ b/sim/falling_edge_detector/makefile_structure.sources @@ -0,0 +1,19 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/d_ff_rtl.vhd \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/incrementer/makefile b/sim/incrementer/makefile new file mode 100644 index 0000000..54e7a63 --- /dev/null +++ b/sim/incrementer/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = incrementer + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/incrementer/makefile.sources b/sim/incrementer/makefile.sources new file mode 100644 index 0000000..8766f99 --- /dev/null +++ b/sim/incrementer/makefile.sources @@ -0,0 +1,23 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/resolver_structure.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/cntupdn_rtl.vhd \ +../../src/incrementer_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/makefile b/sim/makefile new file mode 100644 index 0000000..6e7bd40 --- /dev/null +++ b/sim/makefile @@ -0,0 +1,87 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author(s) : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure shown at +## the end of this file. +## ---------------------------------------------------------------------------- + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make mproject" to create a new modelsim project only' + @echo ' "make compile" to compile all VHDL sources in batch mode' + @echo ' "make modelsim" to start modelsim with graphical user interface' + @echo ' "make sim" to start modelsim gui with the top testbench of the project' + @echo ' "make clean" to remove all generated files' + +mproject : mproject_created + +mproject_created : $(SOURCE_FILES) + # create modelsim project + rm -rf ./modelsim_sources.tcl + for source_file in $(SOURCE_FILES); do \ + echo project addfile $$source_file >> modelsim_sources.tcl; \ + done + vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f" + touch mproject_created + +compile: ./work/_vmake + +./work/_vmake: mproject_created + vsim -c -do "project open $(PROJECT); project calculateorder; quit -f" + grep Error transcript; if [ $$? -eq 0 ] ; then rm -rf work/_vmake; exit 1; fi + + +modelsim: mproject_created + vsim -i -do "project open $(PROJECT)" & + +sim: ./work/_vmake + vsim -i -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" & + +clean: + rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl mproject_created + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/mux2to1/makefile b/sim/mux2to1/makefile new file mode 100644 index 0000000..c655d61 --- /dev/null +++ b/sim/mux2to1/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = mux2to1 + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/mux2to1/makefile.sources b/sim/mux2to1/makefile.sources new file mode 100644 index 0000000..880fac4 --- /dev/null +++ b/sim/mux2to1/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_equation.sources b/sim/mux2to1/makefile_equation.sources new file mode 100644 index 0000000..880fac4 --- /dev/null +++ b/sim/mux2to1/makefile_equation.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_rtl.sources b/sim/mux2to1/makefile_rtl.sources new file mode 100644 index 0000000..7dd9c7d --- /dev/null +++ b/sim/mux2to1/makefile_rtl.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_structure.sources b/sim/mux2to1/makefile_structure.sources new file mode 100644 index 0000000..f797190 --- /dev/null +++ b/sim/mux2to1/makefile_structure.sources @@ -0,0 +1,20 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ +../../src/or2gate_equation.vhd \ +../../src/invgate_equation.vhd \ +../../src/mux2to1_structure.vhd \ + +# do not delete this line +# -----------------------------------------------------------------------------
\ No newline at end of file diff --git a/sim/mux2to1/makefile_structure_errors.sources b/sim/mux2to1/makefile_structure_errors.sources new file mode 100644 index 0000000..c412baf --- /dev/null +++ b/sim/mux2to1/makefile_structure_errors.sources @@ -0,0 +1,20 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ +../../src/or2gate_equation.vhd \ +../../src/invgate_equation.vhd \ +../../src/mux2to1_structure_errors.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_truthtable.sources b/sim/mux2to1/makefile_truthtable.sources new file mode 100644 index 0000000..e815b55 --- /dev/null +++ b/sim/mux2to1/makefile_truthtable.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_truthtable.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/pwm/makefile b/sim/pwm/makefile new file mode 100644 index 0000000..962c45a --- /dev/null +++ b/sim/pwm/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = pwm + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/pwm/makefile.sources b/sim/pwm/makefile.sources new file mode 100644 index 0000000..5db2028 --- /dev/null +++ b/sim/pwm/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/pwm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/pwm_incrementer/makefile b/sim/pwm_incrementer/makefile new file mode 100644 index 0000000..54e7a63 --- /dev/null +++ b/sim/pwm_incrementer/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = incrementer + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/pwm_incrementer/makefile.sources b/sim/pwm_incrementer/makefile.sources new file mode 100644 index 0000000..687a731 --- /dev/null +++ b/sim/pwm_incrementer/makefile.sources @@ -0,0 +1,24 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/resolver_structure.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/cntupdn_rtl.vhd \ +../../src/incrementer_structure.vhd \ +../../src/pwm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/resolver/makefile b/sim/resolver/makefile new file mode 100644 index 0000000..ac0a168 --- /dev/null +++ b/sim/resolver/makefile @@ -0,0 +1,68 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = resolver + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/cntupdn_rtl.vhd \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/resolver/makefile.sources b/sim/resolver/makefile.sources new file mode 100644 index 0000000..272943f --- /dev/null +++ b/sim/resolver/makefile.sources @@ -0,0 +1,21 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/resolver_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/src/a_falling_edge_detector_rtl.vhd b/src/a_falling_edge_detector_rtl.vhd new file mode 100644 index 0000000..117c3f1 --- /dev/null +++ b/src/a_falling_edge_detector_rtl.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Module : rtl +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: detects a falling edge of input signal x_i +-- and produces a high-active signal for one clock period at +-- output fall_o +-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--| +-- x_i -----|___________________________________|----------- +-- fall_o ________|-----|______________________________________ +-- +-- rtl model based on two flip flops with output logic +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ARCHITECTURE rtl OF falling_edge_detector IS + + SIGNAL q0, q1 : std_ulogic; -- D-Type Flip-Flop outputs + +BEGIN + + dflipflop_0 : q0 <= '0' WHEN (rst_ni = '0') ELSE + x_i WHEN rising_edge(clk_i); + + dflipflop_1 : q1 <= '0' WHEN (rst_ni = '0') ELSE + q0 WHEN rising_edge(clk_i); + + output_logic : fall_o <= ; -- fill in the correct equation here + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/adcintf.vhd b/src/adcintf.vhd new file mode 100644 index 0000000..c5ae405 --- /dev/null +++ b/src/adcintf.vhd @@ -0,0 +1,98 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- ADC (Analog to Digital Converter) Interface +-- Shifts in 16 bits and provides the data in parallel +-- When all 16 bits are shifted in, the valid_o output is set to "1" for one clock cycle + +entity adcintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + valid_o : out std_ulogic; + data_o : out std_ulogic_vector(15 downto 0); + start_i : in std_ulogic; + ser_dat_i : in std_ulogic); +end; + +architecture rtl of adcintf is + type state_t is (idle_s, shift_s, done_s); + signal state, new_state : state_t; + signal idx : integer range 0 to 15; + signal data : unsigned(15 downto 0); + signal idx_inc : std_ulogic; + signal idx_reset : std_ulogic; + signal data_shift : std_ulogic; +begin + + seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + data <= (others => '0'); + state <= idle_s; + elsif rising_edge(clk_i) then + if data_shift = '1' then + data <= shift_left(data,1); + data(0) <= ser_dat_i; + end if; + if idx_reset = '1' then + idx <= 0; + elsif idx_inc = '1' and idx < 15 then + idx <= idx + 1; + end if; + state <= new_state; + end if; + end process seq_p; + + statem_comb_p : process(state, idx, start_i, en_i) + begin + idx_inc <= '0'; + idx_reset <= '0'; + new_state <= state; + data_shift <= '0'; + valid_o <= '0'; + case state is + when idle_s => + if start_i = '1' and en_i = '1' then + new_state <= shift_s; + idx_reset <= '1'; + end if; + when shift_s => + if en_i = '1' then + idx_inc <= '1'; + data_shift <= '1'; + if idx = 15 then + new_state <= done_s; + end if; + end if; + when done_s => + valid_o <= '1'; + new_state <= idle_s; + when others => + new_state <= idle_s; + end case; + end process statem_comb_p; + + data_o <= std_ulogic_vector(data); + +end; -- architecture + + diff --git a/src/and2gate_equation.vhd b/src/and2gate_equation.vhd new file mode 100644 index 0000000..9c7f0f2 --- /dev/null +++ b/src/and2gate_equation.vhd @@ -0,0 +1,35 @@ +-------------------------------------------------------------------------------
+-- Module : and2gate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-input AND Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY and2gate IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ y_o : OUT std_ulogic -- data output y
+ );
+END and2gate;
+
+ARCHITECTURE equation OF and2gate IS
+
+BEGIN
+
+ y_o <= a_i AND b_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/audio.vhd b/src/audio.vhd new file mode 100644 index 0000000..9a6ad17 --- /dev/null +++ b/src/audio.vhd @@ -0,0 +1,156 @@ +--Copyright 2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; + +entity audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); +end; + +architecture struct of audio is + + component i2c_sub is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic + ); + end component; + + component adcintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + valid_o : out std_ulogic; + data_o : out std_ulogic_vector(15 downto 0); + start_i : in std_ulogic; + ser_dat_i : in std_ulogic); + end component; + + component dacintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + load_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + en_i : in std_ulogic; + ser_dat_o : out std_ulogic); + end component; + + component bclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_o : out std_ulogic; + bclk_falling_edge_en_o : out std_ulogic); + end component; + + component fsgen is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_falling_edge_en_i : in std_ulogic; + fs_o : out std_ulogic); + end component; + + component mclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + mclk_o : out std_ulogic); + end component; + + signal framesync : std_ulogic; + signal bclk_falling_edge_en : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + i2c_sub_i0 : i2c_sub + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + i2c_clk_o => i2c_sclk_o, + i2c_dat_o => i2c_dat_o, + i2c_dat_i => i2c_dat_i); + + mclk_i0 : mclk + port map( + clk_i => clk_i, + reset_ni => reset_ni, + mclk_o => aud_xck_o); + + bclk_i0 : bclk + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + bclk_o => aud_bclk_o, + bclk_falling_edge_en_o => bclk_falling_edge_en); + + fsgen_i0 : fsgen + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + bclk_falling_edge_en_i => bclk_falling_edge_en, + fs_o => framesync); + + dacintf_i0 : dacintf + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_i => framesync, + data_i => dac_data_i, + en_i => bclk_falling_edge_en, + ser_dat_o => aud_dacdat_o); + + adcintf_i0 : adcintf + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + valid_o => adc_valid_o, + data_o => adc_data_o, + start_i => framesync, + en_i => bclk_falling_edge_en, + ser_dat_i => aud_adcdat_i); + + aud_daclrck_o <= framesync; + aud_adclrck_o <= framesync; + + dac_strobe_o <= framesync and bclk_falling_edge_en; + +end; -- architecture + + diff --git a/src/bclk.vhd b/src/bclk.vhd new file mode 100644 index 0000000..4d72539 --- /dev/null +++ b/src/bclk.vhd @@ -0,0 +1,79 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Bitclock generator + +entity bclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_o : out std_ulogic; + bclk_falling_edge_en_o : out std_ulogic); +end; + +architecture rtl of bclk is + constant max_count : integer := 7; + signal clk_counter : integer range 0 to max_count; + signal bclk_rising_edge_en : std_ulogic; + signal bclk_falling_edge_en : std_ulogic; +begin + + bclk_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + clk_counter <= 0; + elsif rising_edge(clk_i) then + if clk_counter = max_count then + clk_counter <= 0; + else + clk_counter <= clk_counter + 1; + end if; + end if; + end process bclk_cnt_p; + + edge_comb_p : process(clk_counter) + begin + bclk_rising_edge_en <= '0'; + bclk_falling_edge_en <= '0'; + if clk_counter = max_count then + bclk_rising_edge_en <= '1'; + end if; + if clk_counter = max_count / 2 then + bclk_falling_edge_en <= '1'; + end if; + end process edge_comb_p; + + bclk_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + bclk_o <= '0'; + elsif rising_edge(clk_i) then + if bclk_rising_edge_en = '1' then + bclk_o <= '1'; + elsif bclk_falling_edge_en = '1' then + bclk_o <= '0'; + end if; + end if; + end process bclk_p; + + bclk_falling_edge_en_o <= bclk_falling_edge_en; + +end; -- architecture + + diff --git a/src/binto7segment_truthtable.vhd b/src/binto7segment_truthtable.vhd new file mode 100644 index 0000000..e0be505 --- /dev/null +++ b/src/binto7segment_truthtable.vhd @@ -0,0 +1,63 @@ +------------------------------------------------------------------------------- +-- Module : binto7segment +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: binary-to-7-segment decoder +-- function modelled as a truth table +-- using a selected signal assignment +-- segments get illuminated by a low-active signal +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY binto7segment IS + PORT (bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0) + ); +END binto7segment; + +ARCHITECTURE truthtable OF binto7segment IS + + -- seven-segment positions + -- + -- segment positions input vector index segment name + -- a 0 => a + -- --- 1 => b + -- f | | b 2 => c + -- --- <- g 3 => d + -- e | | c 4 => e + -- --- 5 => f + -- d 6 => g + +BEGIN + + decoder : WITH bin_i SELECT + segments_o <= + -- outputs: | inputs: + -------------------------------------------- + -- index | number displayed + -- 6543210 | + -------------------------------------------- + "1000000" WHEN "0000", -- 0 + "1111001" WHEN "0001", -- 1 + "0100100" WHEN "0010", -- 2 + "0110000" WHEN "0011", -- 3 + "0001001" WHEN "0100", -- 4 + "0010010" WHEN "0101", -- 5 + "0000010" WHEN "0110", -- 6 + "0111000" WHEN "0111", -- 7 + "0000000" WHEN "1000", -- 8 + "0010000" WHEN "1001", -- 9 + "0000110" WHEN OTHERS; -- displays Symbol 'E' for ERROR + +END truthtable; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntdn_rtl.vhd b/src/cntdn_rtl.vhd new file mode 100644 index 0000000..7ce14ea --- /dev/null +++ b/src/cntdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- and a terminal count output: tc = 1 when count = 0 +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic + ); +END cntdn; + +ARCHITECTURE rtl OF cntdn IS + + +BEGIN + + incrementer : + + state_register : + + counter_output : + + terminal_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntdnmodm_rtl.vhd b/src/cntdnmodm_rtl.vhd new file mode 100644 index 0000000..51809a4 --- /dev/null +++ b/src/cntdnmodm_rtl.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Module : cntdnmodm +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Modulo-m n-Bit Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +-- additionally, a high_active output signal tc_o is produced, +-- when the counter reaches it's minimum value +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntdnmodm IS + GENERIC ( + n : natural := 4; -- counter width + m : natural := 10); -- modulo value + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(n-1 DOWNTO 0); + tc_o : OUT std_ulogic + ); +END cntdnmodm; + +ARCHITECTURE rtl OF cntdnmodm IS + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + +BEGIN + + -- includes decrementer and modulo logic + next_state_logic : next_state <= to_unsigned(m-1, n) WHEN current_state = 0 ELSE + current_state - 1; + + state_register : + + counter_output : + + terminal_count : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntupdn_rtl.vhd b/src/cntupdn_rtl.vhd new file mode 100644 index 0000000..5f022e3 --- /dev/null +++ b/src/cntupdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntupdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up/Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- mode_i = 0 -> count down +-- mode_i = 1 -> count up +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + mode_i : IN std_ulogic; -- mode_i = 0 -> count down + -- mode_i = 1 -> count up + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupdn; + +ARCHITECTURE rtl OF cntupdn IS + + +BEGIN + + de_incrementer : + + state_register : + + counter_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntupen_rtl.vhd b/src/cntupen_rtl.vhd new file mode 100644 index 0000000..2c68a73 --- /dev/null +++ b/src/cntupen_rtl.vhd @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------- +-- Module : cntupen +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up-Counter +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupen; + +ARCHITECTURE rtl OF cntupen IS + + -- datatype unsigned is defined in package numeric_std + SIGNAL next_state, current_state : unsigned(3 DOWNTO 0); + +BEGIN + + -- package numeric_std overloads operator '+' + -- for arguments of different types, here: unsigned and integer + incrementer : next_state <= current_state + 1; + + + -- synthesisable construct of a d-type register with synchronrous enable + state_register : current_state <= "0000" WHEN rst_ni = '0' ELSE + next_state WHEN rising_edge(clk_i) AND (en_pi = '1'); + + + -- type conversion from unsignd to std_ulogic_vector necessary + counter_output : count_o <= std_ulogic_vector(current_state); + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/d_ff_rtl.vhd b/src/d_ff_rtl.vhd new file mode 100644 index 0000000..af06a3e --- /dev/null +++ b/src/d_ff_rtl.vhd @@ -0,0 +1,39 @@ +------------------------------------------------------------------------------- +-- Module : d_ff +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: D-Type Flip-Flop +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY d_ff IS + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + d_i : IN std_ulogic; + q_o : OUT std_ulogic + ); +END d_ff; + +ARCHITECTURE rtl OF d_ff IS + +BEGIN + + dflipflop_p : q_o <= '0' WHEN (rst_ni = '0') ELSE + d_i WHEN rising_edge(clk_i); + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/dacintf.vhd b/src/dacintf.vhd new file mode 100644 index 0000000..87c48fa --- /dev/null +++ b/src/dacintf.vhd @@ -0,0 +1,60 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- DAC (Digital to Analog Converter) Interface +-- Loads a word in parallel and shifts it out as serial bit stream +-- The data needs to be shifted out twice. This is required as +-- the audio interface needs stereo data. + +entity dacintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + load_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + en_i : in std_ulogic; + ser_dat_o : out std_ulogic); +end; + +architecture rtl of dacintf is + signal idx : integer range 0 to 31; + signal data : unsigned(15 downto 0); +begin + + load_and_shift_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + data <= (others => '0'); + elsif rising_edge(clk_i) then + if load_i = '1' and en_i = '1' then + data <= unsigned(data_i); + idx <= 0; + elsif en_i = '1' and idx < 31 then + data <= rotate_left(data,1); + idx <= idx + 1; + end if; + end if; + end process load_and_shift_p; + + ser_dat_o <= data(15); + +end; -- architecture + + diff --git a/src/de1_adc_rtl.vhd b/src/de1_adc_rtl.vhd new file mode 100644 index 0000000..d82c892 --- /dev/null +++ b/src/de1_adc_rtl.vhd @@ -0,0 +1,111 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- PLL for 100 MHz speed +library altera_mf; +use altera_mf.all; + +entity de1_adc is + port ( CLOCK_50 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + KEY0 : in std_ulogic; + DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual + DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + POWER_ON : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + ADC_DA : in std_ulogic_vector(13 downto 0); + ADC_DB : in std_ulogic_vector(13 downto 0); + ADC_OTR_A : in std_ulogic; + ADC_OTR_B : in std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs +end entity; + +architecture rtl of de1_adc is + + -- Altera PLL + component altpll + generic ( + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; +-- clk0_phase_shift : STRING; +-- compensate_clock : STRING; + inclk0_input_frequency : natural; +-- intended_device_family : STRING; +-- lpm_hint : STRING; +-- lpm_type : STRING; + operation_mode : string; + port_inclk0 : string; + port_clk0 : string + ); + port ( + clk : out std_logic_vector (5 downto 0); + inclk : in std_logic_vector (1 downto 0) + ); + end component; + + signal pll_inclk : std_logic_vector(1 downto 0); + signal pll_outclk : std_logic_vector(5 downto 0); + + signal clk,rst_n : std_ulogic; + signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0); + +begin + + pll_i0 : altpll + generic map ( + clk0_divide_by => 10, + clk0_duty_cycle => 50, + clk0_multiply_by => 13, +-- clk0_phase_shift => "0", +-- compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + operation_mode => "NORMAL", + port_inclk0 => "PORT_USED", + port_clk0 => "PORT_USED" + ) + port map ( + inclk => pll_inclk, + clk => pll_outclk + ); + + pll_inclk(0) <= CLOCK_50; + pll_inclk(1) <= '0'; + clk <= pll_outclk(0); + --clk <= CLOCK_50; + + rst_n <= KEY0; + LEDR <= "00000000" & ADC_OTR_A & ADC_OTR_B when rising_edge(clk); + + DAC_MODE <= '1'; --dual port + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + + dac_a_dat <= (others => '0') when rst_n = '0' else adc_a_dat when falling_edge(clk); + dac_b_dat <= (others => '0') when rst_n = '0' else adc_b_dat when falling_edge(clk); + + DAC_DA <= dac_a_dat; + DAC_DB <= dac_b_dat; + + -- ADC Section + ADC_CLK_A <= clk; + ADC_CLK_B <= clk; + ADC_OEB_A <= '0'; + ADC_OEB_B <= '0'; + POWER_ON <= '1'; + + adc_a_dat <= (others => '0') when rst_n = '0' else ADC_DA when rising_edge(clk); + adc_b_dat <= (others => '0') when rst_n = '0' else ADC_DB when rising_edge(clk); + +end architecture rtl; diff --git a/src/de1_add1_structure.vhd b/src/de1_add1_structure.vhd new file mode 100644 index 0000000..5c12d59 --- /dev/null +++ b/src/de1_add1_structure.vhd @@ -0,0 +1,51 @@ +------------------------------------------------------------------------------- +-- Module : de1_add1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add1 on a DE1 prototype board +-- connecting device under test (DUT) add1 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_add1 IS + PORT ( + SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic_vector(1 DOWNTO 0) -- LED Red[1:0] + ); +END de1_add1; + +ARCHITECTURE structure OF de1_add1 IS + + COMPONENT add1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + ci_i : IN std_ulogic; + sum_o : OUT std_ulogic; + co_o : OUT std_ulogic); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : add1 + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + ci_i => SW(2), + sum_o => LEDR(0), + co_o => LEDR(1) + ); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_add4_structure.vhd b/src/de1_add4_structure.vhd new file mode 100644 index 0000000..bbd75ab --- /dev/null +++ b/src/de1_add4_structure.vhd @@ -0,0 +1,103 @@ +------------------------------------------------------------------------------- +-- Module : de1_add4 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add4 on a DE1 prototype board +-- connecting device under test (DUT) add4 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_add4 IS + PORT ( + SW : IN std_ulogic_vector(8 DOWNTO 0); -- Toggle Switch[8:0] + LEDR : OUT std_ulogic_vector(8 DOWNTO 0); -- LED Red[8:0] + LEDG : OUT std_ulogic_vector(4 DOWNTO 0); -- LED Green[3:0] + HEX0 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 0 + HEX1 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 1 + HEX2 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 2 + + -- Ports for measurement of longest path through module + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + GPO_1 : OUT std_ulogic_vector(1 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[0] = CLOCK_50 + -- GPO_1[1] = co_o + + ); +END de1_add4; + +ARCHITECTURE structure OF de1_add4 IS + + COMPONENT binto7segment + PORT ( + bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0)); + END COMPONENT; + + COMPONENT add4 + PORT ( + a_i : IN std_ulogic_vector(3 DOWNTO 0); + b_i : IN std_ulogic_vector(3 DOWNTO 0); + ci_i : IN std_ulogic; + sum_o : OUT std_ulogic_vector(3 DOWNTO 0); + co_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL a : std_ulogic_vector(3 DOWNTO 0); + SIGNAL b : std_ulogic_vector(3 DOWNTO 0); + SIGNAL ci : std_ulogic; + SIGNAL sum : std_ulogic_vector(3 DOWNTO 0); + SIGNAL co : std_ulogic; + +BEGIN + + -- Modifications for measurement of longest path through module + GPO_1(0) <= CLOCK_50; + GPO_1(1) <= co; + -- use the following line for Tpd measurement + -- ci <= CLOCK_50; -- tpd of add4 module only + + -- connecting switches to operands + ci <= SW(0); -- use this line, if connected by SW(0) + a <= SW(4 DOWNTO 1); + b <= SW(8 DOWNTO 5); + + -- connecting operands to LEDs + LEDR(0) <= SW(0); + LEDR(4 DOWNTO 1) <= SW(4 DOWNTO 1); + LEDR(8 DOWNTO 5) <= SW(8 DOWNTO 5); + + -- connecting device under test with peripheral elements + DUT : add4 + PORT MAP ( + a_i => a, + b_i => b, + ci_i => ci, + sum_o => sum, + co_o => co); + + -- connecting results to LEDs and HEX displays + LEDG(3 DOWNTO 0) <= sum; + LEDG(4) <= co; + + operand_a : binto7segment + PORT MAP ( + bin_i => a, + segments_o => HEX0); + + operand_b : binto7segment + PORT MAP ( -- fill in the missing components here ... + + + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_audio.vhd b/src/de1_audio.vhd new file mode 100644 index 0000000..f01a9a7 --- /dev/null +++ b/src/de1_audio.vhd @@ -0,0 +1,118 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_logic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_audio is + + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + component ringbuf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0)); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data, + dac_strobe_o => dac_strobe); + + ringbuf_i0 : ringbuf + port map ( + clk_i => clk, + reset_ni => reset_n, + en_i => adc_valid, + data_i => adc_data, + data_o => dac_data); + + LEDR(9 downto 0) <= std_ulogic_vector(abs(signed(dac_data(15 downto 6)))); + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture + + diff --git a/src/de1_binto7segment_structure.vhd b/src/de1_binto7segment_structure.vhd new file mode 100644 index 0000000..b4fbd79 --- /dev/null +++ b/src/de1_binto7segment_structure.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Module : de1_binto7segment +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module binto7segment on a DE1 prototype board +-- connecting device under test (DUT) binto7segment +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_binto7segment IS + PORT ( + SW : IN std_ulogic_vector(3 DOWNTO 0); -- Toggle Switch[3:0] + LEDR : OUT std_ulogic_vector(3 DOWNTO 0); -- LED Red[3:0] + HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0 + ); +END de1_binto7segment; + +ARCHITECTURE structure OF de1_binto7segment IS + + COMPONENT binto7segment + PORT ( + bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0)); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : binto7segment + PORT MAP ( + bin_i => SW, + segments_o => HEX0); + + -- connect switches to red LEDs + LEDR <= SW; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_cntdn_structure.vhd b/src/de1_cntdn_structure.vhd new file mode 100644 index 0000000..d420996 --- /dev/null +++ b/src/de1_cntdn_structure.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- Module : de1_cntdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module cntdn on a DE1 prototype board +-- connecting device under test (DUT) cntdn +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_cntdn IS + PORT ( + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + KEY : IN std_ulogic_vector(1 DOWNTO 0); -- KEY[1:0] + -- KEY[0] = rst_ni + -- KEY[1] = en_pi + GPO_1 : OUT std_ulogic_vector(5 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[3:0] = count_o + -- GPO_1[4] = tc_o + -- GPO_1[5] = clk_i + ); +END de1_cntdn; + +ARCHITECTURE structure OF de1_cntdn IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + +BEGIN + + -- connecting clock generator master clock of synchronous system + clk_i <= CLOCK_50; + GPO_1(5) <= clk_i; -- to measure clk signal + + -- connecting asynchronous system reset to digital system + rst_ni <= KEY(0); + + -- count enable input is high-active, KEY(1) ist low-aktive, therefore ... + -- ... if KEY1 is released, high signal is produced + en_pi <= KEY(1); + + + -- connecting device under test with peripheral elements + DUT : ENTITY work.cntdn(rtl) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- connecting count value to GPIO1 + GPO_1(3 DOWNTO 0) <= count_o; + GPO_1(4) <= tc_o; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_cntdnmodm_structure.vhd b/src/de1_cntdnmodm_structure.vhd new file mode 100644 index 0000000..d76c5f3 --- /dev/null +++ b/src/de1_cntdnmodm_structure.vhd @@ -0,0 +1,111 @@ +------------------------------------------------------------------------------- +-- Module : de1_cntdnmodm +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module cntdnmodm on a DE1 prototype board +-- connecting device under test (DUT) cntdnmodm +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_cntdnmodm IS + PORT ( + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + KEY : IN std_ulogic_vector(1 DOWNTO 0); -- KEY[1:0] + -- KEY[0] = rst_ni + -- KEY[1] = en_pi + GPO_1 : OUT std_ulogic_vector(7 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[3:0] = count_o + -- GPO_1[4] = tc_o + -- GPO_1[5] = clk_i + -- GPO_1[6] = tc_mod6_o + -- GPO_1[7] = tc_100hz_o + ); +END de1_cntdnmodm; + +ARCHITECTURE structure OF de1_cntdnmodm IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + + SIGNAL tc_mod6_o : std_ulogic; + SIGNAL tc_100hz_o : std_ulogic; + +BEGIN + + -- connecting clock generator master clock of synchronous system + clk_i <= CLOCK_50; + GPO_1(5) <= clk_i; -- to measure clk signal + + -- connecting asynchronous system reset to digital system + rst_ni <= KEY(0); + + -- count enable input is high-active, KEY(1) ist low-aktive, therefore ... + -- ... if KEY1 is released, high signal is produced + en_pi <= KEY(1); + + + -- connecting device under test with peripheral elements + DUT : ENTITY work.cntdnmodm + GENERIC MAP ( + n => 4, + m => 10) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- 3-bit modulo-6 down counter + mod6_count : ENTITY work.cntdnmodm + GENERIC MAP ( + n => 3, + m => 6) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => OPEN, + tc_o => tc_mod6_o); + + -- instantiate and parameterise the generics to + -- create a frequency of 100 Hz at its output signal tc_100hz_o + -- declare the necessary signals count_modxxx_o and tc_100hz_o + ----------------------------------------------------------------------------- +-- prescaler : cntdnmodm +-- GENERIC MAP ( +-- n => +-- m => ) +-- PORT MAP ( + ----------------------------------------------------------------------------- + + -- connecting count value to GPIO1 + GPO_1(3 DOWNTO 0) <= count_o; + GPO_1(4) <= tc_o; + GPO_1(6) <= tc_mod6_o; + GPO_1(7) <= tc_100hz_o; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_dac_rtl.vhd b/src/de1_dac_rtl.vhd new file mode 100644 index 0000000..c1c90bf --- /dev/null +++ b/src/de1_dac_rtl.vhd @@ -0,0 +1,109 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- PLL for 100 MHz speed +library altera_mf; +use altera_mf.all; + +entity de1_dac is + port ( CLOCK_50 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + KEY0 : in std_ulogic; + DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual + DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + POWER_ON : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs +end entity; + +architecture rtl of de1_dac is + + -- Altera PLL + component altpll + generic ( + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; +-- clk0_phase_shift : STRING; +-- compensate_clock : STRING; + inclk0_input_frequency : natural; +-- intended_device_family : STRING; +-- lpm_hint : STRING; +-- lpm_type : STRING; + operation_mode : string; + port_inclk0 : string; + port_clk0 : string + ); + port ( + clk : out std_logic_vector (5 downto 0); + inclk : in std_logic_vector (1 downto 0) + ); + end component; + + signal pll_inclk : std_logic_vector(1 downto 0); + signal pll_outclk : std_logic_vector(5 downto 0); + + signal clk,rst_n : std_ulogic; + signal cnt : unsigned(13 downto 0); + signal phase_inc : unsigned(9 downto 0); + signal dac_a_reg, dac_a_next, dac_b_reg : unsigned(13 downto 0); + +begin + + pll_i0 : altpll + generic map ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, +-- clk0_phase_shift => "0", +-- compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + operation_mode => "NORMAL", + port_inclk0 => "PORT_USED", + port_clk0 => "PORT_USED" + ) + port map ( + inclk => pll_inclk, + clk => pll_outclk + ); + + pll_inclk(0) <= CLOCK_50; + pll_inclk(1) <= '0'; + + clk <= pll_outclk(0); + rst_n <= '0' when KEY0 = '0' else '1' when rising_edge (clk); + LEDR <= SW; + + DAC_MODE <= '1'; --dual port + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + + phase_inc <= unsigned(SW(9 downto 1) & '0'); + + cnt <= (others => '0') when rst_n = '0' else cnt+phase_inc when rising_edge(clk); + + dac_a_next <= (others => '1') when cnt = 0 else (others => '0'); + dac_a_reg <= (others => '0') when rst_n = '0' else dac_a_next when falling_edge(clk); + dac_b_reg <= (others => '0') when rst_n = '0' else cnt when falling_edge(clk); + DAC_DA <= std_ulogic_vector(dac_a_reg); + DAC_DB <= std_ulogic_vector(dac_b_reg); + + -- ADC Section - switch off everything + ADC_CLK_A <= '0'; + ADC_CLK_B <= '0'; + ADC_OEB_A <= '1'; + ADC_OEB_B <= '1'; + POWER_ON <= '1'; + +end architecture rtl; diff --git a/src/de1_matlab_audio.vhd b/src/de1_matlab_audio.vhd new file mode 100644 index 0000000..4d7e613 --- /dev/null +++ b/src/de1_matlab_audio.vhd @@ -0,0 +1,126 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_matlab_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + SW: in std_ulogic_vector(9 downto 0); + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_logic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_matlab_audio is + + -- Matlab generated toplevel + component ml_audio is + port (clk : in std_logic; + rst_n : in std_logic; + clk_enable : in std_logic; + ce_out : out std_logic; + switches_i : in std_logic_vector(9 downto 0); + audio_i : in std_logic_vector(15 downto 0); + audio_o : out std_logic_vector(15 downto 0)); + end component; + + -- Wolfson AudioCodec Interface block + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data : std_logic_vector(15 downto 0); + signal adc_data, dac_data_reg : std_ulogic_vector(15 downto 0); + signal ml_audio_out_valid : std_ulogic; + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + ml_audio_i0 : ml_audio + port map ( + clk => clk, + rst_n => reset_n, + clk_enable => adc_valid, + ce_out => ml_audio_out_valid, + switches_i => std_logic_vector(SW), + audio_i => std_logic_vector(adc_data), + audio_o => dac_data); + + dac_data_reg <= std_ulogic_vector(dac_data) when rising_edge(clk) and ml_audio_out_valid = '1'; + + -- Wolfson Audio Codec + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data_reg, + dac_strobe_o => dac_strobe); + + LEDR <= SW; + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture diff --git a/src/de1_mux2to1_structure.vhd b/src/de1_mux2to1_structure.vhd new file mode 100644 index 0000000..33c1257 --- /dev/null +++ b/src/de1_mux2to1_structure.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Module : de1_mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add1 on a DE1 prototype board +-- connecting device under test (DUT) add1 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_mux2to1 IS + PORT ( + SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic -- LED Red[0] + ); +END de1_mux2to1; + +ARCHITECTURE structure OF de1_mux2to1 IS + + COMPONENT mux2to1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : mux2to1 + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + sel_i => SW(2), + y_o => LEDR); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_sta.vhd b/src/de1_sta.vhd new file mode 100644 index 0000000..91a93aa --- /dev/null +++ b/src/de1_sta.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity de1_sta is + port ( + CLOCK_50 : in std_ulogic; + x_i : in unsigned(7 downto 0); + y_o : out unsigned(x_i'range) + ); +end de1_sta; + +architecture rtl of de1_sta is + +signal a,b,c,d : unsigned(x_i'range); +signal sum : unsigned(x_i'range); +signal clk : std_ulogic; + +begin + +clk <= CLOCK_50; + +sum <= a + b + c + d; + +y_o <= sum when rising_edge(clk); + +a <= x_i when rising_edge(clk); +b <= a when rising_edge(clk); +c <= b when rising_edge(clk); +d <= c when rising_edge(clk); + +end architecture; diff --git a/src/de1_tone.vhd b/src/de1_tone.vhd new file mode 100644 index 0000000..eff30f9 --- /dev/null +++ b/src/de1_tone.vhd @@ -0,0 +1,119 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_tone is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_logic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_tone is + + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + component tone is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + switches_i : in std_ulogic_vector(9 downto 0); + dv_i : in std_ulogic; + audio_i : in std_ulogic_vector(15 downto 0); + audio_o : out std_ulogic_vector(15 downto 0)); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data, + dac_strobe_o => dac_strobe); + + tone_i0 : tone + port map ( + clk => clk, + rst_n => reset_n, + dv_i => adc_valid, + audio_i => adc_data, + audio_o => dac_data, + switches_i => SW); + + LEDR(9 downto 0) <= SW; + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture + + diff --git a/src/e_falling_edge_detector.vhd b/src/e_falling_edge_detector.vhd new file mode 100644 index 0000000..db0cb16 --- /dev/null +++ b/src/e_falling_edge_detector.vhd @@ -0,0 +1,34 @@ +------------------------------------------------------------------------------- +-- Module : falling_edge_detector +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: detects a falling edge of input signal x_i +-- and produces a high-active signal for one clock period at +-- output fall_o +-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--| +-- x_i -----|___________________________________|----------- +-- fall_o ________|-----|______________________________________ +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY falling_edge_detector IS + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + x_i : IN std_ulogic; + fall_o : OUT std_ulogic + ); +END falling_edge_detector; + + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/fsgen.vhd b/src/fsgen.vhd new file mode 100644 index 0000000..e15deca --- /dev/null +++ b/src/fsgen.vhd @@ -0,0 +1,56 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Frame Sync Generator +-- The framesync is active for one bitclock cycle + +entity fsgen is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_falling_edge_en_i : in std_ulogic; + fs_o : out std_ulogic); +end; + +architecture rtl of fsgen is + constant max_count : integer := 127; + signal counter : integer range 0 to max_count; +begin + + fs_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + counter <= 0; + fs_o <= '0'; + elsif rising_edge(clk_i) then + if bclk_falling_edge_en_i = '1' then + fs_o <= '0'; + if counter = max_count then + counter <= 0; + fs_o <= '1'; + else + counter <= counter + 1; + end if; + end if; + end if; + end process fs_cnt_p; + +end; -- architecture + + diff --git a/src/i2c.vhd b/src/i2c.vhd new file mode 100644 index 0000000..f60cdbe --- /dev/null +++ b/src/i2c.vhd @@ -0,0 +1,245 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- I2C or 2-Wire Bus +-- To start a transaction, pull the data line to 'L' while the clock is still 'H' +-- 7 Bits Address +-- 1 Bit R/W (0 = Write, 1 = Read) +-- 1 Bit ACK (from Slave 0 if o.k.) +-- 8 Bits Data 15..8 +-- 1 Bit Ack from slave (0 if o.k.) +-- 8 Bits Data 7..0 +-- 1 Bit Ack from slave (0 if o.k.) + + +entity i2c is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_i: in std_ulogic; + data_i: in std_ulogic_vector(23 downto 0); + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + busy_o: out std_ulogic + ); +end; + +architecture rtl of i2c is + + -- Clock divider section + constant fd_c : integer := 50000000/20000/2; -- 50 MHz system clock, 20 kHz I2C clock + signal clk_cnt : integer range 0 to fd_c; + signal clk_cnt_reset, clk_cnt_done : std_ulogic; + + -- i2c data register index + signal idx : integer range 0 to 27; + signal idx_inc : std_ulogic; + signal idx_reset : std_ulogic; + + -- i2c registers with and without data for the acknowledgment section + -- In cycle 8, 17 and 26 there is an i2c acknowledgement cycle where the master + -- drives Z and the slave will drive "0" when everything is o.k. + -- The input data from the interface is without these acknowledgement bits + signal load_i2c_reg_without_ack : std_ulogic; + signal i2c_reg_without_ack : std_ulogic_vector(23 downto 0); + signal i2c_reg_with_ack : std_ulogic_vector(0 to 27); + + -- Statemachine + type state_t is (idle_s, start_s, data_hold_s, data_s, clock_high_s, stop_s); + signal state, next_state : state_t; + + -- Selection for the i2c output data + type i2c_dat_sel_t is (sel_old, sel_reg, sel_one, sel_zero); + signal i2c_dat_sel : i2c_dat_sel_t; + + type i2c_clk_sel_t is (sel_old, sel_one, sel_zero); + signal i2c_clk_sel : i2c_clk_sel_t; + + signal i2c_clk : std_ulogic; + signal i2c_clk_new : std_ulogic; + signal i2c_dat : std_ulogic; + signal i2c_dat_new : std_ulogic; + +begin + + -- i2c register with ack build from i2c without ack + -- i2c data is transmitted msb first, so bus direction is changed also + i2c_reg_with_ack(0 to 7) <= i2c_reg_without_ack(23 downto 16); + i2c_reg_with_ack(8) <= '1'; + i2c_reg_with_ack(9 to 16) <= i2c_reg_without_ack(15 downto 8); + i2c_reg_with_ack(17) <= '1'; + i2c_reg_with_ack(18 to 25) <= i2c_reg_without_ack(7 downto 0); + i2c_reg_with_ack(26) <= '1'; + i2c_reg_with_ack(27) <= '0'; + + -- This process counts the clocks for reducing the clock speed + -- of the i2c clock + clk_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + clk_cnt <= 0; + elsif rising_edge(clk_i) then + if clk_cnt < fd_c then + clk_cnt <= clk_cnt + 1; + end if; + if clk_cnt_reset = '1' then + clk_cnt <= 0; + end if; + end if; + end process clk_cnt_p; + + clk_cnt_done <= '1' when clk_cnt = fd_c else '0'; + + -- This is the index for the i2c register. + i2c_idx_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + elsif rising_edge(clk_i) then + if idx_inc = '1' and idx < 27 then + idx <= idx + 1; + end if; + if idx_reset = '1' then + idx <= 0; + end if; + end if; + end process i2c_idx_p; + + -- This are the registered outputs for the i2c clock and data + i2c_out_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + i2c_clk <= '1'; + i2c_dat <= '1'; + elsif rising_edge(clk_i) then + i2c_dat <= i2c_dat_new; + i2c_clk <= i2c_clk_new; + end if; + end process i2c_out_p; + + -- The i2c register without ack data + i2c_data_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + i2c_reg_without_ack <= (others => '0'); + elsif rising_edge(clk_i) then + if load_i2c_reg_without_ack = '1' then + i2c_reg_without_ack <= data_i; + end if; + end if; + end process i2c_data_p; + + -- i2c data selection process + i2c_dat_sel_p : process(i2c_dat_sel, i2c_reg_with_ack, i2c_dat, idx) + begin + case i2c_dat_sel is + when sel_old => i2c_dat_new <= i2c_dat; + when sel_reg => i2c_dat_new <= i2c_reg_with_ack(idx); + when sel_one => i2c_dat_new <= '1'; + when sel_zero => i2c_dat_new <= '0'; + when others => i2c_dat_new <= '0'; + end case; + end process i2c_dat_sel_p; + + -- i2c clock selection process + i2c_clk_sel_p : process(i2c_clk, i2c_clk_sel) + begin + case i2c_clk_sel is + when sel_old => i2c_clk_new <= i2c_clk; + when sel_one => i2c_clk_new <= '1'; + when sel_zero => i2c_clk_new <= '0'; + when others => i2c_clk_new <= '0'; + end case; + end process i2c_clk_sel_p; + + -- Sequential process for the statemachine + statem_seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + state <= idle_s; + elsif rising_edge(clk_i) then + state <= next_state; + end if; + end process statem_seq_p; + + statem_comb_p: process(state, load_i, idx, clk_cnt_done) + begin + load_i2c_reg_without_ack<= '0'; + idx_inc <= '0'; + idx_reset <= '0'; + clk_cnt_reset <= '0'; + busy_o <= '1'; + i2c_dat_sel <= sel_old; + i2c_clk_sel <= sel_old; + next_state <= state; + case state is + when idle_s => + busy_o <= '0'; + i2c_clk_sel <= sel_one; + i2c_dat_sel <= sel_one; + if load_i = '1' then + load_i2c_reg_without_ack <= '1'; + clk_cnt_reset <= '1'; + idx_reset <= '1'; + next_state <= start_s; + i2c_dat_sel <= sel_zero; + end if; + when start_s => + if clk_cnt_done = '1' then + next_state <= data_hold_s; + clk_cnt_reset <= '1'; + i2c_clk_sel <= sel_zero; + end if; + when data_hold_s => + next_state <= data_s; + i2c_dat_sel <= sel_reg; + when data_s => + if clk_cnt_done = '1' then + next_state <= clock_high_s; + i2c_clk_sel <= sel_one; + clk_cnt_reset <= '1'; + end if; + when clock_high_s => + if clk_cnt_done = '1' then + if idx = 27 then -- last bit transmitted + i2c_dat_sel <= sel_one; + next_state <= stop_s; + else + idx_inc <= '1'; + i2c_clk_sel <= sel_zero; + next_state <= data_hold_s; + end if; + clk_cnt_reset <= '1'; + end if; + when stop_s => + if clk_cnt_done = '1' then + next_state <= idle_s; + end if; + when others => + next_state <= idle_s; + end case; + end process statem_comb_p; + + i2c_clk_o <= i2c_clk; + i2c_dat_o <= i2c_dat; + +end; -- architecture + + diff --git a/src/i2c_sub.vhd b/src/i2c_sub.vhd new file mode 100644 index 0000000..e71ff39 --- /dev/null +++ b/src/i2c_sub.vhd @@ -0,0 +1,79 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_sub is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + i2c_clk_o: out std_ulogic); +end; + +architecture struct of i2c_sub is + +component i2c is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_i: in std_ulogic; + data_i: in std_ulogic_vector(23 downto 0); + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + busy_o: out std_ulogic + ); +end component; + +component i2c_write is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_o: out std_ulogic; + data_o: out std_ulogic_vector(23 downto 0); + busy_i: in std_ulogic); +end component; + + signal load, busy : std_ulogic; + signal data : std_ulogic_vector(23 downto 0); + +begin + + i2c_i0 : i2c + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_i => load, + data_i => data, + i2c_clk_o => i2c_clk_o, + i2c_dat_o => i2c_dat_o, + i2c_dat_i => i2c_dat_i, + busy_o => busy); + + i2_write_i0 : i2c_write + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_o => load, + data_o => data, + busy_i => busy); + +end; -- architecture + + diff --git a/src/i2c_write.vhd b/src/i2c_write.vhd new file mode 100644 index 0000000..338a3a7 --- /dev/null +++ b/src/i2c_write.vhd @@ -0,0 +1,98 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_write is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_o: out std_ulogic; + data_o: out std_ulogic_vector(23 downto 0); + busy_i: in std_ulogic); +end; + +architecture rtl of i2c_write is + constant num_regs_c : integer := 12; + type state_t is (start_s, wait_s, done_s); + signal state, next_state : state_t; + signal counter : integer range 0 to num_regs_c-1; + signal counter_enable : std_ulogic; + type data_array_t is array(0 to num_regs_c-1) of std_ulogic_vector(23 downto 0); + + constant data_array : data_array_t := ( + X"341200", -- Set Inactive + X"341E00", -- Reset the Device + X"34001A", -- Left Line In / Mute off / Volume + X"34021A", -- Right Line In + X"34046F", -- Headphone Left + X"34066F", -- Headphone Right + X"340815", -- Analog path control (MIC to ADC, DAC to output, MIC Boost) + X"340A00", -- Digital path control + X"340C61", -- Power Down Control (Everything switched on) + X"340E13", -- Digital Audio Interface Format (Slave Mode, DSP Mode, 16 Bit) + X"341000", -- Sampling Control (48 kHz Sampling frequency, Normal Mode) + X"341201"); -- Active Control (Activate) + +begin + + seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + state <= start_s; + counter <= 0; + elsif rising_edge(clk_i) then + state <= next_state; + if counter_enable = '1' then + if counter < num_regs_c - 1 then + counter <= counter + 1; + else + counter <= 0; + end if; + end if; + end if; + end process seq_p; + + data_o <= data_array(counter); + + process(state, counter, busy_i) + begin + load_o <= '0'; + counter_enable <= '0'; + next_state <= state; + case state is + when start_s => + load_o <= '1'; + next_state <= wait_s; + when wait_s => + if busy_i = '0' then + if counter = num_regs_c-1 then + next_state <= done_s; + --counter_enable <= '1'; + else + next_state <= start_s; + counter_enable <= '1'; + end if; + end if; + when others => + next_state <= state; + end case; + end process; + +end; -- architecture + + diff --git a/src/invgate_equation.vhd b/src/invgate_equation.vhd new file mode 100644 index 0000000..69e920e --- /dev/null +++ b/src/invgate_equation.vhd @@ -0,0 +1,34 @@ +-------------------------------------------------------------------------------
+-- Module : invgate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Inverter Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY invgate IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ y_o : OUT std_ulogic -- data output y
+ );
+END invgate;
+
+ARCHITECTURE equation OF invgate IS
+
+BEGIN
+
+ y_o <= NOT a_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mclk.vhd b/src/mclk.vhd new file mode 100644 index 0000000..5da923d --- /dev/null +++ b/src/mclk.vhd @@ -0,0 +1,48 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Master Clock Generator +-- Generate 12.5 MHz from 50 MHz by dividing by 4 +-- Audio Codec expects 12.288 MHz, so we are slightly higher + +entity mclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + mclk_o : out std_ulogic); +end; + +architecture rtl of mclk is + signal mclk : unsigned(1 downto 0); +begin + + mclk_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + mclk <= to_unsigned(0, mclk'length); + elsif rising_edge(clk_i) then + mclk <= mclk + 1; + end if; + end process mclk_p; + + mclk_o <= mclk(1); + +end; -- architecture + + diff --git a/src/memory.vhd b/src/memory.vhd new file mode 100644 index 0000000..e50d687 --- /dev/null +++ b/src/memory.vhd @@ -0,0 +1,54 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This VHDL memory description will result in FPGA memory usage. +-- The EPC2C20 series provides a total of 52 M4K memory blocks +-- Each M4K memory block contains 4608 Bits. The following configurations are supported: +-- 4K 1, 2K 2, 1K 4, 512 8, 512 9, 256 16, 256 18 +-- The maximum is therefore 52 x 256 = 13312 samples. + +entity memory is + port ( + clk_i : in std_ulogic; + we_i : in std_ulogic; + waddr_i : in unsigned(12 downto 0); + raddr_i : in unsigned(12 downto 0); + wdata_i : in std_ulogic_vector(15 downto 0); + rdata_o : out std_ulogic_vector(15 downto 0) + ); +end; + +architecture rtl of memory is + type ram_t is array(0 to 2 ** 13 - 1) of std_ulogic_vector(15 downto 0); + signal ram : ram_t; +begin + + mem_p : process(clk_i) + begin + if rising_edge(clk_i) then + if we_i = '1' then + ram(to_integer(waddr_i)) <= wdata_i; + end if; + rdata_o <= ram(to_integer(raddr_i)); + end if; + end process mem_p; + +end; -- architecture + + diff --git a/src/mux2to1_equation.vhd b/src/mux2to1_equation.vhd new file mode 100644 index 0000000..0fddb6a --- /dev/null +++ b/src/mux2to1_equation.vhd @@ -0,0 +1,40 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by boolean equation
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE equation OF mux2to1 IS
+
+BEGIN
+
+ y_o <= (sel_i AND a_i) OR (NOT sel_i AND b_i);
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_rtl.vhd b/src/mux2to1_rtl.vhd new file mode 100644 index 0000000..c6447dd --- /dev/null +++ b/src/mux2to1_rtl.vhd @@ -0,0 +1,42 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by a conditional signal assignment
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE rtl OF mux2to1 IS
+
+BEGIN
+
+ y_o <= a_i WHEN sel_i = '1' ELSE
+ b_i WHEN sel_i = '0' ELSE
+ 'X';
+
+END rtl;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_structure.vhd b/src/mux2to1_structure.vhd new file mode 100644 index 0000000..3ff0c97 --- /dev/null +++ b/src/mux2to1_structure.vhd @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled as structure of basic logic gates
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE structure OF mux2to1 IS
+
+ COMPONENT invgate
+ PORT (
+ a_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ COMPONENT and2gate
+ PORT (
+ a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ COMPONENT or2gate
+ PORT (
+ a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ SIGNAL p0, p1 : std_ulogic;
+ SIGNAL p2 : std_ulogic;
+
+BEGIN
+
+ inv_gate_1 : invgate
+ PORT MAP (
+ a_i => sel_i,
+ y_o => p2);
+
+ and2_gate_1 : and2gate
+ PORT MAP (
+ a_i => a_i,
+ b_i => sel_i,
+ y_o => p0);
+
+ and2_gate_2 : and2gate
+ PORT MAP (
+ a_i => b_i,
+ b_i => p2,
+ y_o => p1);
+
+ or2_gate_1 : or2gate
+ PORT MAP (
+ a_i => p0,
+ b_i => p1,
+ y_o => y_o);
+
+-- inv_gate_1 : invgate PORT MAP (sel_i, p2);
+
+-- and2_gate_1 : and2gate PORT MAP (a_i, sel_i, p0);
+
+-- and2_gate_2 : and2gate PORT MAP (b_i, p2, p1);
+
+-- or2_gate_1 : or2gate PORT MAP (p0, p1, y_o);
+
+END structure;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_structure_errors.vhd b/src/mux2to1_structure_errors.vhd new file mode 100644 index 0000000..0b33968 --- /dev/null +++ b/src/mux2to1_structure_errors.vhd @@ -0,0 +1,79 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled as structure of basic logic gates
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ sel_i : IN std_ulogic;
+-- y_o : OUT std_ulogic; -- kein ; nach letztem Signal
+ y_o : OUT std_ulogic
+ );
+END mux21;
+
+
+ARCHITECTURE structure OF mux2to1 IS
+
+ COMPONENT invgate
+ PORT (
+ a_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ COMPONENT or2gate
+ PORT (
+ a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ y_o : std_ulogic);
+ END COMPONENT;
+
+ SIGNAL p1 : std_ulogic;
+ SIGNAL p2 : std_ulogic;
+ SIGNAL p3 : std_ulogic;
+
+BEGIN
+
+ inv_gate_1 : invgate
+ PORT MAP (
+ a_i => sel_i,
+ y_o <= p2);
+
+
+ and2_gate_1 : and2gate
+ PORT MAP (
+ a_i => a_i,
+ b_i => p2
+ y_o => p0);
+
+ and2_gate_2 : and2gate
+ PORT MAP (
+ a_i => b_i,
+ b_i => sel_i,
+ y_o => p1);
+
+ or2_gate_1 : or2gate
+ PORT MAP (
+ a_i => p0,
+ b_i => p1,
+ y_o => p3);
+
+
+END struct
+
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_truthtable.vhd b/src/mux2to1_truthtable.vhd new file mode 100644 index 0000000..ff84c61 --- /dev/null +++ b/src/mux2to1_truthtable.vhd @@ -0,0 +1,54 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by a truth table
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE truthtable OF mux2to1 IS
+
+ SIGNAL inputs_s : std_ulogic_vector(2 DOWNTO 0); -- temp input vector
+
+BEGIN
+
+ inputs_s <= (sel_i, b_i, a_i); -- concatenate single signals to a vector
+
+ tt : WITH inputs_s SELECT -- truthtable
+ y_o <=
+ '0' WHEN "000",
+ '0' WHEN "001",
+ '1' WHEN "010",
+ '1' WHEN "011",
+ '0' WHEN "100",
+ '1' WHEN "101",
+ '0' WHEN "110",
+ '1' WHEN "111",
+ 'X' WHEN OTHERS;
+
+END truthtable;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/or2gate_equation.vhd b/src/or2gate_equation.vhd new file mode 100644 index 0000000..13795fb --- /dev/null +++ b/src/or2gate_equation.vhd @@ -0,0 +1,18 @@ +-------------------------------------------------------------------------------
+-- Module : or2gate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-input OR Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
diff --git a/src/play_rtl.vhd b/src/play_rtl.vhd new file mode 100644 index 0000000..8452236 --- /dev/null +++ b/src/play_rtl.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------ +-- module : play +------------------------------------------------------------------ +-- author : Friedrich Beckmann +-- company : university of applied sciences augsburg +------------------------------------------------------------------ +-- description: Statemachine for LED game +-- +------------------------------------------------------------------ +-- revisions : 0.1 - +------------------------------------------------------------------ + +-- 5 LED outputs +-- One one-second enable input +-- KEY input with preceding rising_edge detector + +-- step LED4 LED3 LED2 LED1 LED0 +-- 1 x - - - - +-- 2 - x - - - +-- 3 - - x - - +-- 4 - - - x - +-- 5 - - - - x +-- 6 x - - - - +-- ... this pattern continues +-- If LED2 is on and KEY is pressed then the pattern continues as follows +-- 1 x - - - - +-- 2 - - - - x +-- ... this pattern continues until +-- KEY is pressed again. Then the previous pattern restarts from LED 2 + +library ieee; +use ieee.std_logic_1164.all; + +entity play is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + onesec_i : in std_ulogic; + key_i : in std_ulogic; + led_o : out std_ulogic_vector(4 downto 0)); +end play; + +architecture rtl of play is + + type state_t is (start_s,one_s,chance_s,four_s,last_s,hit0_s,hit1_s); + signal current_state,next_state : state_t; + +begin + + current_state <= start_s when rst_n = '0' else next_state when rising_edge(clk); + + next_p : process(current_state, onesec_i, key_i) + begin + next_state <= current_state; + led_o <= "00000"; + case current_state is + when start_s => + led_o <= "10000"; + if onesec_i = '1' then + next_state <= one_s; + end if; + when one_s => + led_o <= "01000"; + if onesec_i = '1' then + next_state <= chance_s; + end if; + when chance_s => + led_o <= "00100"; + if key_i = '1' then + next_state <= hit0_s; + elsif onesec_i = '1' then + next_state <= four_s; + end if; + when four_s => + led_o <= "00010"; + if onesec_i = '1' then + next_state <= last_s; + end if; + when last_s => + led_o <= "00001"; + if onesec_i = '1' then + next_state <= start_s; + end if; + when hit0_s => + led_o <= "10000"; + if key_i = '1' then + next_state <= chance_s; + elsif onesec_i = '1' then + next_state <= hit1_s; + end if; + when hit1_s => + led_o <= "00001"; + if key_i = '1' then + next_state <= chance_s; + elsif onesec_i = '1' then + next_state <= hit0_s; + end if; + when others => null; + end case; + end process; + +end architecture rtl; diff --git a/src/ringbuf.vhd b/src/ringbuf.vhd new file mode 100644 index 0000000..7c45815 --- /dev/null +++ b/src/ringbuf.vhd @@ -0,0 +1,74 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Ring Buffer stores samples in a circular buffer +-- The read buffer pointer is one buffer entry ahead +-- of the write buffer pointer. + +entity ringbuf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0)); +end; + +architecture rtl of ringbuf is + +component memory is + port ( + clk_i : in std_ulogic; + we_i : in std_ulogic; + waddr_i : in unsigned(12 downto 0); + raddr_i : in unsigned(12 downto 0); + wdata_i : in std_ulogic_vector(15 downto 0); + rdata_o : out std_ulogic_vector(15 downto 0) + ); +end component; + + signal raddr, waddr : unsigned(12 downto 0); + +begin + + mem_i0 : memory + port map ( + clk_i => clk_i, + we_i => en_i, + raddr_i => raddr, + waddr_i => waddr, + rdata_o => data_o, + wdata_i => data_i); + + buffer_pointer_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + waddr <= to_unsigned(0, 13); + raddr <= to_unsigned(1, 13); + elsif rising_edge(clk_i) then + if en_i = '1' then + raddr <= raddr + 1; + waddr <= waddr + 1; + end if; + end if; + end process buffer_pointer_p; + +end; -- architecture + + diff --git a/src/t_cntdn.vhd b/src/t_cntdn.vhd new file mode 100644 index 0000000..42888c6 --- /dev/null +++ b/src/t_cntdn.vhd @@ -0,0 +1,123 @@ +------------------------------------------------------------------------------- +-- Module : t_cntdn +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "cntdn" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY t_cntdn IS +END t_cntdn; + +ARCHITECTURE tbench OF t_cntdn IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + DUT : cntdn + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- clock generation + clock_proc : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset, always necessary at the beginning of a simulation + -- initial reset, always necessary at the beginning of a simulation + ----------------------------------------------------------------------------- + -- Following a verification plan: + -- ------------------------------ + -- 1. t = 0 ns: activate asynchronous reset + -- 2. t = 10 ns: deactivate asynchronous reset + ----------------------------------------------------------------------------- + reset : rst_ni <= '0', '1' AFTER period; + + stimuli_p : PROCESS + + BEGIN + + --------------------------------------------------------------------------- + -- ... continuing with the verification plan: + --------------------------------------------------------------------------- + WAIT UNTIL rising_edge(rst_ni); -- wait for reset + -- ... is deactivated + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 2. activate enable + -- 3. Wait for a full counting cycle + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- 4. After another five periods: Deactivate Enable + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 5. After another three periods: Activate Enable + -- 6. Simulate another complete counting cycle + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 7. Simulate until tc_o = 1 again + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + + clken_p <= false; -- switch clock generator off + + WAIT; -- suspend proces + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_cntdnmodm.vhd b/src/t_cntdnmodm.vhd new file mode 100644 index 0000000..5b3b9e3 --- /dev/null +++ b/src/t_cntdnmodm.vhd @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------- +-- Module : t_cntdnmodm +------------------------------------------------------------------------------- +-- Author : <johann.faerber@hs-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2013 <johann.faerber@hs-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "cntdnmodm" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY t_cntdnmodm IS +END t_cntdnmodm; + +ARCHITECTURE tbench OF t_cntdnmodm IS + + COMPONENT cntdnmodm + GENERIC ( + n : natural; + m : natural); + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(n-1 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + -- component generics + CONSTANT n : natural := 4; + CONSTANT m : natural := 10; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(n-1 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + + SIGNAL count_mod6_o : std_ulogic_vector(2 DOWNTO 0); + SIGNAL tc_mod6_o : std_ulogic; + + SIGNAL count_mod500e3_o : std_ulogic_vector(18 DOWNTO 0); + SIGNAL tc_100hz_o : std_ulogic; + + + -- definition of a clock period + CONSTANT period : time := 20 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + +BEGIN -- tbench + + -- component instantiation + MUV : cntdnmodm + GENERIC MAP ( + n => n, + m => m) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + mod6_count : cntdnmodm + GENERIC MAP ( + n => 3, + m => 6) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_mod6_o, + tc_o => tc_mod6_o); + + -- instantiate and parameterise the generics to + -- create a frequency of 100 Hz at its output signal tc_100hz_o + -- declare the necessary signals count_modxxx_o and tc_100hz_o + ----------------------------------------------------------------------------- +-- prescaler : cntdnmodm +-- GENERIC MAP ( +-- n => +-- m => ) +-- PORT MAP ( + ----------------------------------------------------------------------------- + + + -- clock generation + clock_p : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset + reset : rst_ni <= '1', '0' AFTER period, + '1' AFTER 2 * period; + + -- process for stimuli generation + stimuli_p : PROCESS + + BEGIN + + WAIT UNTIL rising_edge(rst_ni); -- wait for reset + + en_pi <= '1'; -- activate counter + + + -- wait for a period of tc_o ---------------------------------------------- + WAIT UNTIL rising_edge(tc_o); + WAIT UNTIL falling_edge(tc_o); + + WAIT UNTIL count_o = X"5"; + + en_pi <= '0'; -- stop counter ... + WAIT FOR 3* period; -- ... for 3 periods + + en_pi <= '1'; -- activate counter + + -- wait for a period of tc_mod6_o ----------------------------------------- + WAIT UNTIL rising_edge(tc_mod6_o); + WAIT UNTIL falling_edge(tc_mod6_o); + --------------------------------------------------------------------------- + + + -- wait for a period of tc_100hz_o ---------------------------------------- + + --------------------------------------------------------------------------- + + + -- wait for a period of tc_100hz_o ---------------------------------------- + + --------------------------------------------------------------------------- + + + clken_p <= false; -- switch clock generator off + + WAIT; + END PROCESS; + + + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_de1_audio.vhd b/src/t_de1_audio.vhd new file mode 100644 index 0000000..bfa0f1f --- /dev/null +++ b/src/t_de1_audio.vhd @@ -0,0 +1,88 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity t_de1_audio is +end; + +architecture tbench of t_de1_audio is + +component de1_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_ulogic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0) + ); +end component; + + signal clk, reset_n : std_ulogic; + signal ledr : std_ulogic_vector(9 downto 0); + signal i2c_clk, i2c_dat : std_ulogic; + signal key0 : std_ulogic; + + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + + signal simrun : boolean := true; + +begin + + de1_audio_i0 : de1_audio + port map ( + CLOCK_50 => clk, + KEY0 => reset_n, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + LEDR => ledr); + + clock_p : process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + if not simrun then + wait; + end if; + end process clock_p; + + simrun <= false after 1 ms; + + reset_p : process + begin + reset_n <= '0'; + wait for 15 us; + reset_n <= '1'; + wait; + end process reset_p; + + aud_adcdat <= '1'; + +end; -- architecture diff --git a/src/t_de1_play.vhd b/src/t_de1_play.vhd new file mode 100644 index 0000000..8a2b739 --- /dev/null +++ b/src/t_de1_play.vhd @@ -0,0 +1,100 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity t_de1_play is +end t_de1_play; + +architecture tbench of t_de1_play is + +component de1_play is + port ( + CLOCK_50 : in std_ulogic; -- 50 mhz clock + KEY : in std_ulogic_vector(1 downto 0); -- key(1..0) + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_logic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0) + LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0) + ); +end component; + + -- definition of a clock period + constant period : time := 10 ns; + -- switch for clock generator + signal clken_p : boolean := true; + + + signal clk_i : std_ulogic; + signal rst_ni : std_ulogic; + signal key : std_ulogic; + signal ledr : std_ulogic_vector(4 downto 0); + + signal i2c_clk, i2c_dat : std_ulogic; + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + signal phase : real := 0.0; + signal test_tone : real; + signal test_tone_quantized : signed(15 downto 0); + signal bit_count : integer range 0 to 31; + +begin + + -- clock generation + clock_proc : process + begin + while clken_p loop + clk_i <= '0'; wait for period/2; + clk_i <= '1'; wait for period/2; + end loop; + wait; + end process; + + -- initial reset, always necessary at the beginning of a simulation + reset : rst_ni <= '0', '1' AFTER period; + + stimuli_p : process + begin + key <= '1'; + wait until rst_ni = '1'; + wait for 20*period; + key <= '0'; + wait for 10*period; + key <= '1'; + wait for 30*period; + clken_p <= false; + wait; + end process stimuli_p; + + + de1_play_i0 : de1_play + port map ( + CLOCK_50 => clk_i, + KEY(0) => rst_ni, + KEY(1) => key, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + LEDR => ledr); + + aud_adcdat <= test_tone_quantized(bit_count mod 16); + + -- Test tone generator for simulating the ADC from the audio codec + phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck); + test_tone <= sin(2*3.14*phase); + test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16); + bit_count <= 31 when falling_edge(aud_daclrck) else + 0 when bit_count = 0 else + bit_count - 1 when falling_edge(aud_bclk); + +end tbench; diff --git a/src/t_de1_tone.vhd b/src/t_de1_tone.vhd new file mode 100644 index 0000000..37d9e6b --- /dev/null +++ b/src/t_de1_tone.vhd @@ -0,0 +1,108 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity t_de1_tone is +end; + +architecture tbench of t_de1_tone is + + component de1_tone is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_ulogic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + LEDR : out std_ulogic_vector(9 downto 0) + ); + end component; + + signal clk, reset_n : std_ulogic; + signal ledr : std_ulogic_vector(9 downto 0); + signal i2c_clk, i2c_dat : std_ulogic; + signal key0 : std_ulogic; + + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + + signal simrun : boolean := true; + + signal phase : real := 0.0; + signal test_tone : real; + signal test_tone_quantized : signed(15 downto 0); + signal bit_count : integer range 0 to 31; + signal switches : std_ulogic_vector(9 downto 0); + +begin + + de1_tone_i0 : de1_tone + port map ( + CLOCK_50 => clk, + KEY0 => reset_n, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + SW => switches, + LEDR => ledr); + + clock_p : process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + if not simrun then + wait; + end if; + end process clock_p; + + simrun <= false after 5 ms; + + reset_p : process + begin + reset_n <= '0'; + wait for 15 us; + reset_n <= '1'; + wait; + end process reset_p; + + aud_adcdat <= test_tone_quantized(bit_count mod 16); + + -- Test tone generator for simulating the ADC from the audio codec + phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck); + test_tone <= sin(2*3.14*phase); + test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16); + bit_count <= 31 when falling_edge(aud_daclrck) else + 0 when bit_count = 0 else + bit_count - 1 when falling_edge(aud_bclk); + + + +end; -- architecture diff --git a/src/t_falling_edge_detector.vhd b/src/t_falling_edge_detector.vhd new file mode 100644 index 0000000..9fda089 --- /dev/null +++ b/src/t_falling_edge_detector.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- Module : t_falling_edge_detector +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "falling_edge_detector" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_falling_edge_detector IS +END t_falling_edge_detector; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_falling_edge_detector IS + + COMPONENT falling_edge_detector + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + x_i : IN std_ulogic; + fall_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL x_i : std_ulogic; + SIGNAL fall_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : falling_edge_detector + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + x_i => x_i, + fall_o => fall_o); + + -- clock generation + clock_p : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset, always necessary at the beginning of a simulation + reset : rst_ni <= '0', '1' AFTER period; + + + stimuli_p : PROCESS + BEGIN + + WAIT UNTIL rst_ni = '1'; -- wait until asynchronous reset ... + -- ... is deactivated + --------------------------------------------------------------------------- + + -- create a low-active pulse over a no. of clock periods + --------------------------------------------------------------------------- + x_i <= '1'; -- assign a '1' to x_i + WAIT FOR period; + + x_i <= '0'; -- set input to '0' ... + WAIT UNTIL rising_edge(clk_i); + WAIT UNTIL falling_edge(clk_i); + -- Observer: check, if fall_o is assigned to '1' for one clock period + ASSERT fall_o = '1' REPORT "Error: Expected fall_o = '1' !" SEVERITY failure; + WAIT UNTIL falling_edge(clk_i); + ASSERT fall_o = '0' REPORT "Error: Expected fall_o = '0' !" SEVERITY failure; + WAIT FOR 6 * period; -- ... for a no. of periods + + x_i <= '1'; -- assign a '1' to form a + WAIT FOR 3 * period; -- low active input pulse + --------------------------------------------------------------------------- + + + -- add another low-active input pulse here ... + + + + + + + + + + clken_p <= false; -- switch clock generator off + + WAIT; -- suspend proces + END PROCESS; + + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_mux2to1.vhd b/src/t_mux2to1.vhd new file mode 100644 index 0000000..4d4d118 --- /dev/null +++ b/src/t_mux2to1.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- Module : t_mux2to1 +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "mux2to1" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_mux2to1 IS +END t_mux2to1; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_mux2to1 IS + + COMPONENT mux2to1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + + -- component ports + SIGNAL a_i : std_ulogic; + SIGNAL b_i : std_ulogic; + SIGNAL sel_i : std_ulogic; + SIGNAL y_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : mux2to1 + PORT MAP ( + a_i => a_i, + b_i => b_i, + sel_i => sel_i, + y_o => y_o); + + stimuli_p : PROCESS + + BEGIN + a_i <= '0'; -- set a value to input a_i + b_i <= '0'; -- set a value to input b_i + sel_i <= '0'; -- set a value to input ci_i + WAIT FOR period; -- values are assigned here + + a_i <= '1'; -- change value of a_i + WAIT FOR period; + + a_i <= '0'; -- change value of a_i + b_i <= '1'; -- change value of b_i + WAIT FOR period; + + + -- add the missing stimuli here ... + + + + WAIT; + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/tone_rtl.vhd b/src/tone_rtl.vhd new file mode 100644 index 0000000..815ebb8 --- /dev/null +++ b/src/tone_rtl.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tone is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + switches_i : in std_ulogic_vector(9 downto 0); + dv_i : in std_ulogic; + audio_i : in std_ulogic_vector(15 downto 0); + audio_o : out std_ulogic_vector(15 downto 0)); +end entity; + +architecture rtl of tone is + +begin + +audio_o <= audio_i when rising_edge(clk) and dv_i = '1'; + +end architecture rtl; |