added basic design directory structure

2 files changed, 69 insertions, 0 deletions

diff --git a/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl b/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl
new file mode 100644
index 0000000..81d32b6
--- /dev/null
+++ b/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl
@@ -0,0 +1,16 @@
+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_H14 -to GPO_1[2]
+set_location_assignment PIN_G15 -to GPO_1[3]
+set_location_assignment PIN_E14 -to GPO_1[4]
+set_location_assignment PIN_E15 -to GPO_1[5]
+set_location_assignment PIN_F15 -to GPO_1[6]
+set_location_assignment PIN_G16 -to GPO_1[7]
+# ----------------------------------------------------------------------------
diff --git a/pnr/de1_cntdnmodm/makefile b/pnr/de1_cntdnmodm/makefile
new file mode 100644
index 0000000..72e14e0
--- /dev/null
+++ b/pnr/de1_cntdnmodm/makefile
@@ -0,0 +1,53 @@
+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = cntdnmodm
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+# DE1
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+# DEMMK
+# FAMILY = "MAX II"
+# DEVICE = EPM2210F324C3
+# PROGFILEEXT = pof
+# DE2
+#FAMILY = "Cyclone II"
+#DEVICE = EP2C35F484C7
+#PROGFILEEXT = sof
+# DE0
+#FAMILY = "Cyclone IV E"
+#DEVICE = EP4CE22F17C6
+#PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+