diff options
| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /pnr/de1_pwm | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'pnr/de1_pwm')
| -rw-r--r-- | pnr/de1_pwm/de1_pwm_pins.tcl | 27 | ||||
| -rw-r--r-- | pnr/de1_pwm/makefile | 87 |
2 files changed, 114 insertions, 0 deletions
diff --git a/pnr/de1_pwm/de1_pwm_pins.tcl b/pnr/de1_pwm/de1_pwm_pins.tcl new file mode 100644 index 0000000..1d79959 --- /dev/null +++ b/pnr/de1_pwm/de1_pwm_pins.tcl @@ -0,0 +1,27 @@ +# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_H14 -to GPO_1[2]
+# ----------------------------------------------------------------------------
diff --git a/pnr/de1_pwm/makefile b/pnr/de1_pwm/makefile new file mode 100644 index 0000000..5ed5024 --- /dev/null +++ b/pnr/de1_pwm/makefile @@ -0,0 +1,87 @@ +## ----------------------------------------------------------------------------
+## Script : makefile
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber, Friedrich Beckmann
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+## it is based on a design directory structure described in
+## ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration:
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite:
+# - mandatory design directory structure (see end of file)
+# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = pwm
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+# DE1
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+# DEMMK
+# FAMILY = "MAX II"
+# DEVICE = EPM2210F324C3
+# PROGFILEEXT = pof
+# DE2
+#FAMILY = "Cyclone II"
+#DEVICE = EP2C35F484C7
+#PROGFILEEXT = sof
+# DE0
+#FAMILY = "Cyclone IV E"
+#DEVICE = EP4CE22F17C6
+#PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined.
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description:
+## ------------
+## assumes the following design directory structure as prerequisite
+##
+## DigitaltechnikPraktikum
+## |
+## +---src
+## | and2gate_equation.vhd
+## | invgate_equation.vhd
+## | mux2to1_structure.vhd
+## | or2gate_equation.vhd
+## | t_mux2to1.vhd
+## | de1_mux2to1_structure.vhd
+## |
+## +---sim
+## | | makefile
+## | |
+## | \---mux2to1
+## | makefile
+## | makefile.sources
+## |
+## +---pnr
+## | | makefile
+## | |
+## | \---de1_mux2to1
+## | de1_mux2to1_pins.tcl
+## | makefile
+## |
+## \---scripts
+## de1_pin_assignments_minimumio.csv
+## de1_pin_assignments_minimumio.tcl
+## modelsim.ini
+## quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
|