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| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /sim/resolver/makefile.sources | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'sim/resolver/makefile.sources')
| -rw-r--r-- | sim/resolver/makefile.sources | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/sim/resolver/makefile.sources b/sim/resolver/makefile.sources new file mode 100644 index 0000000..272943f --- /dev/null +++ b/sim/resolver/makefile.sources @@ -0,0 +1,21 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/resolver_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- |