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Diffstat (limited to 'doc/pulse_width_modulator_presentation.md')
-rw-r--r-- | doc/pulse_width_modulator_presentation.md | 70 |
1 files changed, 35 insertions, 35 deletions
diff --git a/doc/pulse_width_modulator_presentation.md b/doc/pulse_width_modulator_presentation.md index d742c03..83cbaf7 100644 --- a/doc/pulse_width_modulator_presentation.md +++ b/doc/pulse_width_modulator_presentation.md @@ -1,8 +1,8 @@ --- -title: Heartbeat Generator +title: Pulse Width Modulator subtitle: VLSI-Design Module - Presentation author: J Färber -date: SS2021 +date: SS2022 --- Overview @@ -20,26 +20,25 @@ Overview Features ======== - * Models QRS-Complex and T-Wave - * Average time values based on 72 bpm - * Enable input for external prescaler - + * Default 8-bit resolution + * 8-bit control word input + * Enable input for external prescaler to control PWM period + Interface Signals ================= -{width=40%} +{width=40%} Functional Description ====================== -Simplification to Digital Pulses +Duty Cycle --------- -{width=20%} - +{width=60%} -{width=80%} +[Reference: Wikipedia - Pulse Width Modulation](https://en.wikipedia.org/wiki/Pulse-width_modulation) Functional Description @@ -48,37 +47,37 @@ Functional Description Conceptional RTL Diagram --------------- -{width=60%} +{width=60%} Simulation Result - Top Level ============================= -{width=80%} +{width=80%} Device Utilization and Performance ================================== ```pure -+------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+-----------------------------------------+ -; Fitter Status ; Successful - Wed Mar 31 11:50:15 2021 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web ; -; Revision Name ; de1_heartbeat_gen ; -; Top-level Entity Name ; de1_heartbeat_gen ; -; Family ; Cyclone II ; -; Device ; EP2C20F484C7 ; -; Timing Models ; Final ; -; Total logic elements ; 50 / 18,752 ( < 1 % ) ; -; Total combinational functions ; 50 / 18,752 ( < 1 % ) ; -; Dedicated logic registers ; 26 / 18,752 ( < 1 % ) ; -; Total registers ; 26 ; -; Total pins ; 15 / 315 ( 5 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 239,616 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; -+------------------------------------+-----------------------------------------+ ++-----------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------+ +; Fitter Status ; Successful - Fri Mar 11 10:39:29 2022 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web; +; Revision Name ; de1_pwm ; +; Top-level Entity Name ; de1_pwm ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 38 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 38 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 21 / 18,752 ( < 1 % ) ; +; Total registers ; 21 ; +; Total pins ; 22 / 315 ( 7 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+----------------------------------------+ ``` Demonstration @@ -87,7 +86,7 @@ Demonstration Prototype Setup --------------- -{width=70%} +{width=70%} Demonstration ============= @@ -95,7 +94,8 @@ Demonstration Test Environment ---------------- - +Measurement Result +----------- |