doc/pulse_width_modulator_presentation.md


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---
title: Pulse Width Modulator
subtitle: VLSI-Design Module - Presentation
author: J Färber
date: SS2022
---

Overview
========

* Features
* Interface Signals
* Block Diagram
* Functional Description
* Simulation Result
* Device Utilization and Performance
* Demonstration
* Questions

Features
========

  * Default 8-bit resolution
  * 8-bit control word input
  * Enable input for external prescaler to control PWM period
  
Interface Signals
=================

![Pulse Width Modulator - Schematic Symbol](images/pwm.svg){width=40%}


Functional Description
======================

Duty Cycle
---------

![Duty Cycle Examples](images/Duty_Cycle_Examples.png){width=60%}

[Reference: Wikipedia - Pulse Width Modulation](https://en.wikipedia.org/wiki/Pulse-width_modulation)


Functional Description
======================

Conceptional RTL Diagram
---------------

![Pulse Width Modulator - Conceptional RTL](images/pwm_conceptional_rtl.svg){width=60%}

Simulation Result - Top Level
=============================

![Pulse Width Modulator - Simulation Result](images/pwm_simwave.png){width=80%}

Device Utilization and Performance
==================================

```pure
+-----------------------------------------------------------------------------+
; Fitter Summary                                                              ;
+------------------------------------+----------------------------------------+
; Fitter Status                      ; Successful - Fri Mar 11 10:39:29 2022  ;
; Quartus II 32-bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web;
; Revision Name                      ; de1_pwm                                ;
; Top-level Entity Name              ; de1_pwm                                ;
; Family                             ; Cyclone II                             ;
; Device                             ; EP2C20F484C7                           ;
; Timing Models                      ; Final                                  ;
; Total logic elements               ; 38 / 18,752 ( < 1 % )                  ;
;     Total combinational functions  ; 38 / 18,752 ( < 1 % )                  ;
;     Dedicated logic registers      ; 21 / 18,752 ( < 1 % )                  ;
; Total registers                    ; 21                                     ;
; Total pins                         ; 22 / 315 ( 7 % )                       ;
; Total virtual pins                 ; 0                                      ;
; Total memory bits                  ; 0 / 239,616 ( 0 % )                    ;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % )                         ;
; Total PLLs                         ; 0 / 4 ( 0 % )                          ;
+------------------------------------+----------------------------------------+
```

Demonstration
=============

Prototype Setup
---------------

![Test Environment on DE1 Prototype Board](images/de1_pwm_schematic.svg){width=70%}

Demonstration
=============

Test Environment
----------------

Measurement Result
-----------


Questions
=========

Thank you for your attention !