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Diffstat (limited to 'pnr/de1_fir/makefile')
| -rwxr-xr-x | pnr/de1_fir/makefile | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/pnr/de1_fir/makefile b/pnr/de1_fir/makefile new file mode 100755 index 0000000..7a271a4 --- /dev/null +++ b/pnr/de1_fir/makefile @@ -0,0 +1,27 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +SIM_PROJECT_NAME = fir +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile |