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## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
SIM_PROJECT_NAME = fir
PROJECT = de1_$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/$(PROJECT)_structure.vhd
include ../makefile
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