aboutsummaryrefslogtreecommitdiff
path: root/sim/fir/makefile.sources
diff options
context:
space:
mode:
Diffstat (limited to 'sim/fir/makefile.sources')
-rwxr-xr-xsim/fir/makefile.sources18
1 files changed, 18 insertions, 0 deletions
diff --git a/sim/fir/makefile.sources b/sim/fir/makefile.sources
new file mode 100755
index 0000000..575e14f
--- /dev/null
+++ b/sim/fir/makefile.sources
@@ -0,0 +1,18 @@
+## ----------------------------------------------------------------------------
+## Script : makefile.sources
+## ----------------------------------------------------------------------------
+## Author : Johann Faerber
+## Company : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+## Attention !!!
+## -------------
+## Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/fir_mac_rtl.vhd \
+../../src/fir_structure.vhd \
+
+# do not delete this line
+# -----------------------------------------------------------------------------