1 files changed, 31 insertions, 14 deletions

diff --git a/src/de1_sta.vhd b/src/de1_sta.vhd
index 91a93aa..2f72da9 100644
--- a/src/de1_sta.vhd
+++ b/src/de1_sta.vhd
@@ -5,28 +5,45 @@ use ieee.numeric_std.all;
 entity de1_sta is
   port (
     CLOCK_50 : in  std_ulogic;
-    x_i      : in  unsigned(7 downto 0);
-    y_o      : out unsigned(x_i'range)
+    KEY0     : in std_ulogic;
+    LEDR     : out std_ulogic_vector(9 downto 0)
     );
 end de1_sta;
 
 architecture rtl of de1_sta is
 
-signal a,b,c,d : unsigned(x_i'range);
-signal sum : unsigned(x_i'range);
-signal clk : std_ulogic;
+function cnt_ones (x : unsigned) return integer is
+  variable cnt : integer range 0 to x'length;
+begin
+  cnt := 0;
+  for i in x'range loop
+    if x(i) = '1' then
+	   cnt := cnt + 1;
+	 end if;
+  end loop;
+  return cnt;
+end function;
+
+signal sum : unsigned(47 downto 0);
+signal clk, rst_n : std_ulogic;
+signal res, res_reg : std_ulogic;
+signal no_of_ones : integer range 0 to sum'length;
+signal no_of_ones_l, no_of_ones_u, no_of_ones_l_reg, no_of_ones_u_reg : integer range 0 to sum'length/2;
 
 begin
+res <= '1' when no_of_ones > sum'length/2 else '0';
+res_reg <= '0' when rst_n = '0' else res when rising_edge(clk);
+sum <= (others => '0') when rst_n = '0' else sum + 1 when rising_edge(clk);
+no_of_ones <= cnt_ones(sum);
+--no_of_ones <= no_of_ones_l_reg + no_of_ones_u_reg;
+LEDR <= (9 downto 1 => '0', 0 => res_reg) when rising_edge(clk);
+
+no_of_ones_u <= cnt_ones(sum(sum'high downto sum'length/2));
+no_of_ones_u_reg <= no_of_ones_u when rising_edge(clk);
+no_of_ones_l <= cnt_ones(sum(sum'length/2-1 downto 0));
+no_of_ones_l_reg <= no_of_ones_l when rising_edge(clk);
 
 clk <= CLOCK_50;
-
-sum <= a + b + c + d;
-
-y_o <= sum when rising_edge(clk);
-
-a <= x_i when rising_edge(clk);
-b <= a when rising_edge(clk);
-c <= b when rising_edge(clk);
-d <= c when rising_edge(clk);
+rst_n <= KEY0;
 
 end architecture;