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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity de1_sta is
port (
CLOCK_50 : in std_ulogic;
KEY0 : in std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)
);
end de1_sta;
architecture rtl of de1_sta is
function cnt_ones (x : unsigned) return integer is
variable cnt : integer range 0 to x'length;
begin
cnt := 0;
for i in x'range loop
if x(i) = '1' then
cnt := cnt + 1;
end if;
end loop;
return cnt;
end function;
signal sum : unsigned(47 downto 0);
signal clk, rst_n : std_ulogic;
signal res, res_reg : std_ulogic;
signal no_of_ones : integer range 0 to sum'length;
signal no_of_ones_l, no_of_ones_u, no_of_ones_l_reg, no_of_ones_u_reg : integer range 0 to sum'length/2;
begin
res <= '1' when no_of_ones > sum'length/2 else '0';
res_reg <= '0' when rst_n = '0' else res when rising_edge(clk);
sum <= (others => '0') when rst_n = '0' else sum + 1 when rising_edge(clk);
no_of_ones <= cnt_ones(sum);
--no_of_ones <= no_of_ones_l_reg + no_of_ones_u_reg;
LEDR <= (9 downto 1 => '0', 0 => res_reg) when rising_edge(clk);
no_of_ones_u <= cnt_ones(sum(sum'high downto sum'length/2));
no_of_ones_u_reg <= no_of_ones_u when rising_edge(clk);
no_of_ones_l <= cnt_ones(sum(sum'length/2-1 downto 0));
no_of_ones_l_reg <= no_of_ones_l when rising_edge(clk);
clk <= CLOCK_50;
rst_n <= KEY0;
end architecture;
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