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-rw-r--r--top_simple/src/top_simple.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/top_simple/src/top_simple.scala b/top_simple/src/top_simple.scala
index ec43fe8..1f8756f 100644
--- a/top_simple/src/top_simple.scala
+++ b/top_simple/src/top_simple.scala
@@ -18,10 +18,10 @@ case class top_simple() extends Component {
}
// The following defines the vhdl and verilog code generation
-object verilog extends App {
+object genverilog extends App {
Config.spinal.generateVerilog(top_simple())
}
-object vhdl extends App {
+object genvhdl extends App {
Config.spinal.generateVhdl(top_simple())
}