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package top_simple
import spinal.core._
// Hardware definition
case class top_simple() extends Component {
val io = new Bundle {
val SW = in Bits(10 bits)
val LEDR = out Bits(10 bits)
val LEDG = out Bits(8 bits)
}
// Remove io_ from the port names in generated vhdl code
noIoPrefix()
io.LEDR := io.SW
io.LEDG := "00000000"
}
// The following defines the vhdl and verilog code generation
object genverilog extends App {
Config.spinal.generateVerilog(top_simple())
}
object genvhdl extends App {
Config.spinal.generateVhdl(top_simple())
}
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