add pwm

4 files changed, 23 insertions, 1 deletions

diff --git a/sim/top_count/makefile.sources b/sim/top_count/makefile.sources
index fd93aea..430c6e1 100644
--- a/sim/top_count/makefile.sources
+++ b/sim/top_count/makefile.sources
@@ -5,4 +5,5 @@ SYN_SOURCE_FILES = \
 ../../src/cnt1sec.vhd \
 ../../src/bin2seg.vhd \
 ../../src/ringcnt.vhd \
+../../src/pwm.vhd \
 ../../src/top_count.vhd
diff --git a/src/pwm.vhd b/src/pwm.vhd
new file mode 100644
index 0000000..b23a170
--- /dev/null
+++ b/src/pwm.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pwm is
+  port (
+    clk   : in std_ulogic;
+    rst_n : in std_ulogic;
+    ctrl_i : in std_ulogic_vector(3 downto 0);
+    pwm_o  : out std_ulogic);
+end entity;
+
+architecture rtl of pwm is
+begin
+
+end architecture rtl; 
+
diff --git a/src/top_count.vhd b/src/top_count.vhd
index 57c6998..0a84349 100644
--- a/src/top_count.vhd
+++ b/src/top_count.vhd
@@ -16,6 +16,7 @@ architecture rtl of top_count is
   signal rst_n   : std_ulogic;
   signal x       : std_ulogic;
   signal en      : std_ulogic;
+  signal pwm     : std_ulogic;
   signal cnt     : std_ulogic_vector(3 downto 0);
 begin
   -- Assign the inputs to signals with reasonable names
@@ -24,6 +25,8 @@ begin
   x <= KEY(1);
 
   cnt <= "0000";
+  en <= '0';
+  pwm <= '0';
   
   bin2seg_inst: entity work.bin2seg
    port map(
@@ -34,7 +37,7 @@ begin
   -- Set the outputs;
   EXP(7 downto 4) <= cnt;
   EXP(3 downto 0) <= (3 => en,
-          2 => x,
+          2 => pwm,
           1 => rst_n,
           0 => clk);
   LEDR <= SW;
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index b8740bd..d162b4d 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -19,6 +19,7 @@ top_count.files = [
     ,'src/ringcnt.vhd'
     ,'src/cntm13.vhd'
     ,'src/cnt1sec.vhd'
+    ,'src/pwm.vhd'
     ,'src/top_count.vhd'
     ,'src/t_top_count.vhd'
     ]
\ No newline at end of file