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| author | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2024-05-27 17:32:24 +0200 |
|---|---|---|
| committer | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2024-05-28 12:31:52 +0200 |
| commit | 2caa12d7f849d5bb5aebed5f306f2def408ae8e3 (patch) | |
| tree | c41f4e9678f4e7141668856d204176388d85964c /src/uart_rx_shift.vhd | |
| parent | 3dd4ccf8e17309ed97e5bdbd8cff6a2855d284fa (diff) | |
uart rx solutionsolutions
Diffstat (limited to 'src/uart_rx_shift.vhd')
| -rw-r--r-- | src/uart_rx_shift.vhd | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/uart_rx_shift.vhd b/src/uart_rx_shift.vhd index 273931c..30a8403 100644 --- a/src/uart_rx_shift.vhd +++ b/src/uart_rx_shift.vhd @@ -11,6 +11,10 @@ entity uart_rx_shift is end entity; architecture rtl of uart_rx_shift is + signal sr, nsr : std_ulogic_vector(7 downto 0); begin + sr <= "00000000" when rst_n = '0' else nsr when rising_edge(clk); + nsr <= ser_i & sr(7 downto 1) when shift_i = '1' else sr; + d_o <= sr; end architecture rtl; |