add top_hex

2 files changed, 76 insertions, 0 deletions

diff --git a/src/bin2seg.vhd b/src/bin2seg.vhd
new file mode 100644
index 0000000..0e56d28
--- /dev/null
+++ b/src/bin2seg.vhd
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- Convert a binary number to control signals for HEX Display
+entity bin2seg is 
+port ( bin_i   : in      std_ulogic_vector(3 downto 0);
+       seg_o   : out     std_ulogic_vector(6 downto 0));  
+end entity;
+
+architecture rtl of bin2seg is 
+
+  -- seven-segment positions
+  -- 
+  -- segment positions    input vector index     segment name
+  --      a                      0            =>     a
+  --     ---                     1            =>     b
+  --  f |   | b                  2            =>     c
+  --     ---   <- g              3            =>     d 
+  --  e |   | c                  4            =>     e 
+  --     ---                     5            =>     f 
+  --      d                      6            =>     g
+
+
+  -- The segment LED will be switched on when the output is '0' and off when
+  -- output is '1'
+  
+begin
+    
+  with bin_i select
+    seg_o <=
+--   gfedcba segment
+    "1000000" when "0000",              -- 0
+    "1111001" when "0001",              -- 1
+    "0100100" when "0010",              -- 2
+    "0110000" when "0011",
+    "0011001" when "0100",
+    "0010010" when "0101",
+    "0000010" when "0110",
+    "1111000" when "0111",
+    "0000000" when "1000",
+    "0010000" when "1001",
+    "0001000" when "1010",
+    "0000011" when "1011",
+    "1000110" when "1100",
+    "0100001" when "1101",              -- 13
+    "0000110" when "1110",              -- 14
+    "0001110" when others;              -- 15
+
+end architecture rtl; 
+
diff --git a/src/top_hex.vhd b/src/top_hex.vhd
new file mode 100644
index 0000000..cfe2d33
--- /dev/null
+++ b/src/top_hex.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top_hex is 
+port ( SW   : in      std_ulogic_vector(9 downto 0);
+       HEX0 : out     std_ulogic_vector(6 downto 0);
+       HEX1 : out     std_ulogic_vector(6 downto 0);
+       HEX2 : out     std_ulogic_vector(6 downto 0);
+       LEDR : out     std_ulogic_vector(9 downto 0));
+end entity;
+
+architecture rtl of top_hex is
+begin
+
+LEDR <= SW;
+
+bin2seg_i0: entity work.bin2seg
+ port map(
+    bin_i => SW(3 downto 0),
+    seg_o => HEX0
+);
+
+HEX1 <= "1111111";
+HEX2 <= "1111111";
+
+end architecture rtl;