diff options
| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /pnr/de1_tone/makefile | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'pnr/de1_tone/makefile')
| -rw-r--r-- | pnr/de1_tone/makefile | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/pnr/de1_tone/makefile b/pnr/de1_tone/makefile new file mode 100644 index 0000000..e9cf6e6 --- /dev/null +++ b/pnr/de1_tone/makefile @@ -0,0 +1,14 @@ +SIM_PROJECT_NAME = de1_tone +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile |