diff options
author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
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committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /src/mux2to1_equation.vhd | |
parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) |
added basic design directory structure
Diffstat (limited to 'src/mux2to1_equation.vhd')
-rw-r--r-- | src/mux2to1_equation.vhd | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/mux2to1_equation.vhd b/src/mux2to1_equation.vhd new file mode 100644 index 0000000..0fddb6a --- /dev/null +++ b/src/mux2to1_equation.vhd @@ -0,0 +1,40 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by boolean equation
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE equation OF mux2to1 IS
+
+BEGIN
+
+ y_o <= (sel_i AND a_i) OR (NOT sel_i AND b_i);
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
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