diff options
| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /src | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'src')
48 files changed, 3764 insertions, 0 deletions
diff --git a/src/a_falling_edge_detector_rtl.vhd b/src/a_falling_edge_detector_rtl.vhd new file mode 100644 index 0000000..117c3f1 --- /dev/null +++ b/src/a_falling_edge_detector_rtl.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Module : rtl +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: detects a falling edge of input signal x_i +-- and produces a high-active signal for one clock period at +-- output fall_o +-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--| +-- x_i -----|___________________________________|----------- +-- fall_o ________|-----|______________________________________ +-- +-- rtl model based on two flip flops with output logic +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ARCHITECTURE rtl OF falling_edge_detector IS + + SIGNAL q0, q1 : std_ulogic; -- D-Type Flip-Flop outputs + +BEGIN + + dflipflop_0 : q0 <= '0' WHEN (rst_ni = '0') ELSE + x_i WHEN rising_edge(clk_i); + + dflipflop_1 : q1 <= '0' WHEN (rst_ni = '0') ELSE + q0 WHEN rising_edge(clk_i); + + output_logic : fall_o <= ; -- fill in the correct equation here + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/adcintf.vhd b/src/adcintf.vhd new file mode 100644 index 0000000..c5ae405 --- /dev/null +++ b/src/adcintf.vhd @@ -0,0 +1,98 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- ADC (Analog to Digital Converter) Interface +-- Shifts in 16 bits and provides the data in parallel +-- When all 16 bits are shifted in, the valid_o output is set to "1" for one clock cycle + +entity adcintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + valid_o : out std_ulogic; + data_o : out std_ulogic_vector(15 downto 0); + start_i : in std_ulogic; + ser_dat_i : in std_ulogic); +end; + +architecture rtl of adcintf is + type state_t is (idle_s, shift_s, done_s); + signal state, new_state : state_t; + signal idx : integer range 0 to 15; + signal data : unsigned(15 downto 0); + signal idx_inc : std_ulogic; + signal idx_reset : std_ulogic; + signal data_shift : std_ulogic; +begin + + seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + data <= (others => '0'); + state <= idle_s; + elsif rising_edge(clk_i) then + if data_shift = '1' then + data <= shift_left(data,1); + data(0) <= ser_dat_i; + end if; + if idx_reset = '1' then + idx <= 0; + elsif idx_inc = '1' and idx < 15 then + idx <= idx + 1; + end if; + state <= new_state; + end if; + end process seq_p; + + statem_comb_p : process(state, idx, start_i, en_i) + begin + idx_inc <= '0'; + idx_reset <= '0'; + new_state <= state; + data_shift <= '0'; + valid_o <= '0'; + case state is + when idle_s => + if start_i = '1' and en_i = '1' then + new_state <= shift_s; + idx_reset <= '1'; + end if; + when shift_s => + if en_i = '1' then + idx_inc <= '1'; + data_shift <= '1'; + if idx = 15 then + new_state <= done_s; + end if; + end if; + when done_s => + valid_o <= '1'; + new_state <= idle_s; + when others => + new_state <= idle_s; + end case; + end process statem_comb_p; + + data_o <= std_ulogic_vector(data); + +end; -- architecture + + diff --git a/src/and2gate_equation.vhd b/src/and2gate_equation.vhd new file mode 100644 index 0000000..9c7f0f2 --- /dev/null +++ b/src/and2gate_equation.vhd @@ -0,0 +1,35 @@ +-------------------------------------------------------------------------------
+-- Module : and2gate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-input AND Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY and2gate IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ y_o : OUT std_ulogic -- data output y
+ );
+END and2gate;
+
+ARCHITECTURE equation OF and2gate IS
+
+BEGIN
+
+ y_o <= a_i AND b_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/audio.vhd b/src/audio.vhd new file mode 100644 index 0000000..9a6ad17 --- /dev/null +++ b/src/audio.vhd @@ -0,0 +1,156 @@ +--Copyright 2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; + +entity audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); +end; + +architecture struct of audio is + + component i2c_sub is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic + ); + end component; + + component adcintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + valid_o : out std_ulogic; + data_o : out std_ulogic_vector(15 downto 0); + start_i : in std_ulogic; + ser_dat_i : in std_ulogic); + end component; + + component dacintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + load_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + en_i : in std_ulogic; + ser_dat_o : out std_ulogic); + end component; + + component bclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_o : out std_ulogic; + bclk_falling_edge_en_o : out std_ulogic); + end component; + + component fsgen is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_falling_edge_en_i : in std_ulogic; + fs_o : out std_ulogic); + end component; + + component mclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + mclk_o : out std_ulogic); + end component; + + signal framesync : std_ulogic; + signal bclk_falling_edge_en : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + i2c_sub_i0 : i2c_sub + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + i2c_clk_o => i2c_sclk_o, + i2c_dat_o => i2c_dat_o, + i2c_dat_i => i2c_dat_i); + + mclk_i0 : mclk + port map( + clk_i => clk_i, + reset_ni => reset_ni, + mclk_o => aud_xck_o); + + bclk_i0 : bclk + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + bclk_o => aud_bclk_o, + bclk_falling_edge_en_o => bclk_falling_edge_en); + + fsgen_i0 : fsgen + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + bclk_falling_edge_en_i => bclk_falling_edge_en, + fs_o => framesync); + + dacintf_i0 : dacintf + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_i => framesync, + data_i => dac_data_i, + en_i => bclk_falling_edge_en, + ser_dat_o => aud_dacdat_o); + + adcintf_i0 : adcintf + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + valid_o => adc_valid_o, + data_o => adc_data_o, + start_i => framesync, + en_i => bclk_falling_edge_en, + ser_dat_i => aud_adcdat_i); + + aud_daclrck_o <= framesync; + aud_adclrck_o <= framesync; + + dac_strobe_o <= framesync and bclk_falling_edge_en; + +end; -- architecture + + diff --git a/src/bclk.vhd b/src/bclk.vhd new file mode 100644 index 0000000..4d72539 --- /dev/null +++ b/src/bclk.vhd @@ -0,0 +1,79 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Bitclock generator + +entity bclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_o : out std_ulogic; + bclk_falling_edge_en_o : out std_ulogic); +end; + +architecture rtl of bclk is + constant max_count : integer := 7; + signal clk_counter : integer range 0 to max_count; + signal bclk_rising_edge_en : std_ulogic; + signal bclk_falling_edge_en : std_ulogic; +begin + + bclk_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + clk_counter <= 0; + elsif rising_edge(clk_i) then + if clk_counter = max_count then + clk_counter <= 0; + else + clk_counter <= clk_counter + 1; + end if; + end if; + end process bclk_cnt_p; + + edge_comb_p : process(clk_counter) + begin + bclk_rising_edge_en <= '0'; + bclk_falling_edge_en <= '0'; + if clk_counter = max_count then + bclk_rising_edge_en <= '1'; + end if; + if clk_counter = max_count / 2 then + bclk_falling_edge_en <= '1'; + end if; + end process edge_comb_p; + + bclk_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + bclk_o <= '0'; + elsif rising_edge(clk_i) then + if bclk_rising_edge_en = '1' then + bclk_o <= '1'; + elsif bclk_falling_edge_en = '1' then + bclk_o <= '0'; + end if; + end if; + end process bclk_p; + + bclk_falling_edge_en_o <= bclk_falling_edge_en; + +end; -- architecture + + diff --git a/src/binto7segment_truthtable.vhd b/src/binto7segment_truthtable.vhd new file mode 100644 index 0000000..e0be505 --- /dev/null +++ b/src/binto7segment_truthtable.vhd @@ -0,0 +1,63 @@ +------------------------------------------------------------------------------- +-- Module : binto7segment +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: binary-to-7-segment decoder +-- function modelled as a truth table +-- using a selected signal assignment +-- segments get illuminated by a low-active signal +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY binto7segment IS + PORT (bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0) + ); +END binto7segment; + +ARCHITECTURE truthtable OF binto7segment IS + + -- seven-segment positions + -- + -- segment positions input vector index segment name + -- a 0 => a + -- --- 1 => b + -- f | | b 2 => c + -- --- <- g 3 => d + -- e | | c 4 => e + -- --- 5 => f + -- d 6 => g + +BEGIN + + decoder : WITH bin_i SELECT + segments_o <= + -- outputs: | inputs: + -------------------------------------------- + -- index | number displayed + -- 6543210 | + -------------------------------------------- + "1000000" WHEN "0000", -- 0 + "1111001" WHEN "0001", -- 1 + "0100100" WHEN "0010", -- 2 + "0110000" WHEN "0011", -- 3 + "0001001" WHEN "0100", -- 4 + "0010010" WHEN "0101", -- 5 + "0000010" WHEN "0110", -- 6 + "0111000" WHEN "0111", -- 7 + "0000000" WHEN "1000", -- 8 + "0010000" WHEN "1001", -- 9 + "0000110" WHEN OTHERS; -- displays Symbol 'E' for ERROR + +END truthtable; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntdn_rtl.vhd b/src/cntdn_rtl.vhd new file mode 100644 index 0000000..7ce14ea --- /dev/null +++ b/src/cntdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- and a terminal count output: tc = 1 when count = 0 +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic + ); +END cntdn; + +ARCHITECTURE rtl OF cntdn IS + + +BEGIN + + incrementer : + + state_register : + + counter_output : + + terminal_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntdnmodm_rtl.vhd b/src/cntdnmodm_rtl.vhd new file mode 100644 index 0000000..51809a4 --- /dev/null +++ b/src/cntdnmodm_rtl.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Module : cntdnmodm +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Modulo-m n-Bit Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +-- additionally, a high_active output signal tc_o is produced, +-- when the counter reaches it's minimum value +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntdnmodm IS + GENERIC ( + n : natural := 4; -- counter width + m : natural := 10); -- modulo value + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(n-1 DOWNTO 0); + tc_o : OUT std_ulogic + ); +END cntdnmodm; + +ARCHITECTURE rtl OF cntdnmodm IS + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + +BEGIN + + -- includes decrementer and modulo logic + next_state_logic : next_state <= to_unsigned(m-1, n) WHEN current_state = 0 ELSE + current_state - 1; + + state_register : + + counter_output : + + terminal_count : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntupdn_rtl.vhd b/src/cntupdn_rtl.vhd new file mode 100644 index 0000000..5f022e3 --- /dev/null +++ b/src/cntupdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntupdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up/Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- mode_i = 0 -> count down +-- mode_i = 1 -> count up +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + mode_i : IN std_ulogic; -- mode_i = 0 -> count down + -- mode_i = 1 -> count up + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupdn; + +ARCHITECTURE rtl OF cntupdn IS + + +BEGIN + + de_incrementer : + + state_register : + + counter_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntupen_rtl.vhd b/src/cntupen_rtl.vhd new file mode 100644 index 0000000..2c68a73 --- /dev/null +++ b/src/cntupen_rtl.vhd @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------- +-- Module : cntupen +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up-Counter +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupen; + +ARCHITECTURE rtl OF cntupen IS + + -- datatype unsigned is defined in package numeric_std + SIGNAL next_state, current_state : unsigned(3 DOWNTO 0); + +BEGIN + + -- package numeric_std overloads operator '+' + -- for arguments of different types, here: unsigned and integer + incrementer : next_state <= current_state + 1; + + + -- synthesisable construct of a d-type register with synchronrous enable + state_register : current_state <= "0000" WHEN rst_ni = '0' ELSE + next_state WHEN rising_edge(clk_i) AND (en_pi = '1'); + + + -- type conversion from unsignd to std_ulogic_vector necessary + counter_output : count_o <= std_ulogic_vector(current_state); + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/d_ff_rtl.vhd b/src/d_ff_rtl.vhd new file mode 100644 index 0000000..af06a3e --- /dev/null +++ b/src/d_ff_rtl.vhd @@ -0,0 +1,39 @@ +------------------------------------------------------------------------------- +-- Module : d_ff +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: D-Type Flip-Flop +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY d_ff IS + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + d_i : IN std_ulogic; + q_o : OUT std_ulogic + ); +END d_ff; + +ARCHITECTURE rtl OF d_ff IS + +BEGIN + + dflipflop_p : q_o <= '0' WHEN (rst_ni = '0') ELSE + d_i WHEN rising_edge(clk_i); + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/dacintf.vhd b/src/dacintf.vhd new file mode 100644 index 0000000..87c48fa --- /dev/null +++ b/src/dacintf.vhd @@ -0,0 +1,60 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- DAC (Digital to Analog Converter) Interface +-- Loads a word in parallel and shifts it out as serial bit stream +-- The data needs to be shifted out twice. This is required as +-- the audio interface needs stereo data. + +entity dacintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + load_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + en_i : in std_ulogic; + ser_dat_o : out std_ulogic); +end; + +architecture rtl of dacintf is + signal idx : integer range 0 to 31; + signal data : unsigned(15 downto 0); +begin + + load_and_shift_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + data <= (others => '0'); + elsif rising_edge(clk_i) then + if load_i = '1' and en_i = '1' then + data <= unsigned(data_i); + idx <= 0; + elsif en_i = '1' and idx < 31 then + data <= rotate_left(data,1); + idx <= idx + 1; + end if; + end if; + end process load_and_shift_p; + + ser_dat_o <= data(15); + +end; -- architecture + + diff --git a/src/de1_adc_rtl.vhd b/src/de1_adc_rtl.vhd new file mode 100644 index 0000000..d82c892 --- /dev/null +++ b/src/de1_adc_rtl.vhd @@ -0,0 +1,111 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- PLL for 100 MHz speed +library altera_mf; +use altera_mf.all; + +entity de1_adc is + port ( CLOCK_50 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + KEY0 : in std_ulogic; + DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual + DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + POWER_ON : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + ADC_DA : in std_ulogic_vector(13 downto 0); + ADC_DB : in std_ulogic_vector(13 downto 0); + ADC_OTR_A : in std_ulogic; + ADC_OTR_B : in std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs +end entity; + +architecture rtl of de1_adc is + + -- Altera PLL + component altpll + generic ( + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; +-- clk0_phase_shift : STRING; +-- compensate_clock : STRING; + inclk0_input_frequency : natural; +-- intended_device_family : STRING; +-- lpm_hint : STRING; +-- lpm_type : STRING; + operation_mode : string; + port_inclk0 : string; + port_clk0 : string + ); + port ( + clk : out std_logic_vector (5 downto 0); + inclk : in std_logic_vector (1 downto 0) + ); + end component; + + signal pll_inclk : std_logic_vector(1 downto 0); + signal pll_outclk : std_logic_vector(5 downto 0); + + signal clk,rst_n : std_ulogic; + signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0); + +begin + + pll_i0 : altpll + generic map ( + clk0_divide_by => 10, + clk0_duty_cycle => 50, + clk0_multiply_by => 13, +-- clk0_phase_shift => "0", +-- compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + operation_mode => "NORMAL", + port_inclk0 => "PORT_USED", + port_clk0 => "PORT_USED" + ) + port map ( + inclk => pll_inclk, + clk => pll_outclk + ); + + pll_inclk(0) <= CLOCK_50; + pll_inclk(1) <= '0'; + clk <= pll_outclk(0); + --clk <= CLOCK_50; + + rst_n <= KEY0; + LEDR <= "00000000" & ADC_OTR_A & ADC_OTR_B when rising_edge(clk); + + DAC_MODE <= '1'; --dual port + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + + dac_a_dat <= (others => '0') when rst_n = '0' else adc_a_dat when falling_edge(clk); + dac_b_dat <= (others => '0') when rst_n = '0' else adc_b_dat when falling_edge(clk); + + DAC_DA <= dac_a_dat; + DAC_DB <= dac_b_dat; + + -- ADC Section + ADC_CLK_A <= clk; + ADC_CLK_B <= clk; + ADC_OEB_A <= '0'; + ADC_OEB_B <= '0'; + POWER_ON <= '1'; + + adc_a_dat <= (others => '0') when rst_n = '0' else ADC_DA when rising_edge(clk); + adc_b_dat <= (others => '0') when rst_n = '0' else ADC_DB when rising_edge(clk); + +end architecture rtl; diff --git a/src/de1_add1_structure.vhd b/src/de1_add1_structure.vhd new file mode 100644 index 0000000..5c12d59 --- /dev/null +++ b/src/de1_add1_structure.vhd @@ -0,0 +1,51 @@ +------------------------------------------------------------------------------- +-- Module : de1_add1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add1 on a DE1 prototype board +-- connecting device under test (DUT) add1 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_add1 IS + PORT ( + SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic_vector(1 DOWNTO 0) -- LED Red[1:0] + ); +END de1_add1; + +ARCHITECTURE structure OF de1_add1 IS + + COMPONENT add1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + ci_i : IN std_ulogic; + sum_o : OUT std_ulogic; + co_o : OUT std_ulogic); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : add1 + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + ci_i => SW(2), + sum_o => LEDR(0), + co_o => LEDR(1) + ); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_add4_structure.vhd b/src/de1_add4_structure.vhd new file mode 100644 index 0000000..bbd75ab --- /dev/null +++ b/src/de1_add4_structure.vhd @@ -0,0 +1,103 @@ +------------------------------------------------------------------------------- +-- Module : de1_add4 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add4 on a DE1 prototype board +-- connecting device under test (DUT) add4 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_add4 IS + PORT ( + SW : IN std_ulogic_vector(8 DOWNTO 0); -- Toggle Switch[8:0] + LEDR : OUT std_ulogic_vector(8 DOWNTO 0); -- LED Red[8:0] + LEDG : OUT std_ulogic_vector(4 DOWNTO 0); -- LED Green[3:0] + HEX0 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 0 + HEX1 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 1 + HEX2 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 2 + + -- Ports for measurement of longest path through module + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + GPO_1 : OUT std_ulogic_vector(1 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[0] = CLOCK_50 + -- GPO_1[1] = co_o + + ); +END de1_add4; + +ARCHITECTURE structure OF de1_add4 IS + + COMPONENT binto7segment + PORT ( + bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0)); + END COMPONENT; + + COMPONENT add4 + PORT ( + a_i : IN std_ulogic_vector(3 DOWNTO 0); + b_i : IN std_ulogic_vector(3 DOWNTO 0); + ci_i : IN std_ulogic; + sum_o : OUT std_ulogic_vector(3 DOWNTO 0); + co_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL a : std_ulogic_vector(3 DOWNTO 0); + SIGNAL b : std_ulogic_vector(3 DOWNTO 0); + SIGNAL ci : std_ulogic; + SIGNAL sum : std_ulogic_vector(3 DOWNTO 0); + SIGNAL co : std_ulogic; + +BEGIN + + -- Modifications for measurement of longest path through module + GPO_1(0) <= CLOCK_50; + GPO_1(1) <= co; + -- use the following line for Tpd measurement + -- ci <= CLOCK_50; -- tpd of add4 module only + + -- connecting switches to operands + ci <= SW(0); -- use this line, if connected by SW(0) + a <= SW(4 DOWNTO 1); + b <= SW(8 DOWNTO 5); + + -- connecting operands to LEDs + LEDR(0) <= SW(0); + LEDR(4 DOWNTO 1) <= SW(4 DOWNTO 1); + LEDR(8 DOWNTO 5) <= SW(8 DOWNTO 5); + + -- connecting device under test with peripheral elements + DUT : add4 + PORT MAP ( + a_i => a, + b_i => b, + ci_i => ci, + sum_o => sum, + co_o => co); + + -- connecting results to LEDs and HEX displays + LEDG(3 DOWNTO 0) <= sum; + LEDG(4) <= co; + + operand_a : binto7segment + PORT MAP ( + bin_i => a, + segments_o => HEX0); + + operand_b : binto7segment + PORT MAP ( -- fill in the missing components here ... + + + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_audio.vhd b/src/de1_audio.vhd new file mode 100644 index 0000000..f01a9a7 --- /dev/null +++ b/src/de1_audio.vhd @@ -0,0 +1,118 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_logic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_audio is + + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + component ringbuf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0)); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data, + dac_strobe_o => dac_strobe); + + ringbuf_i0 : ringbuf + port map ( + clk_i => clk, + reset_ni => reset_n, + en_i => adc_valid, + data_i => adc_data, + data_o => dac_data); + + LEDR(9 downto 0) <= std_ulogic_vector(abs(signed(dac_data(15 downto 6)))); + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture + + diff --git a/src/de1_binto7segment_structure.vhd b/src/de1_binto7segment_structure.vhd new file mode 100644 index 0000000..b4fbd79 --- /dev/null +++ b/src/de1_binto7segment_structure.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Module : de1_binto7segment +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module binto7segment on a DE1 prototype board +-- connecting device under test (DUT) binto7segment +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_binto7segment IS + PORT ( + SW : IN std_ulogic_vector(3 DOWNTO 0); -- Toggle Switch[3:0] + LEDR : OUT std_ulogic_vector(3 DOWNTO 0); -- LED Red[3:0] + HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0 + ); +END de1_binto7segment; + +ARCHITECTURE structure OF de1_binto7segment IS + + COMPONENT binto7segment + PORT ( + bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0)); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : binto7segment + PORT MAP ( + bin_i => SW, + segments_o => HEX0); + + -- connect switches to red LEDs + LEDR <= SW; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_cntdn_structure.vhd b/src/de1_cntdn_structure.vhd new file mode 100644 index 0000000..d420996 --- /dev/null +++ b/src/de1_cntdn_structure.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- Module : de1_cntdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module cntdn on a DE1 prototype board +-- connecting device under test (DUT) cntdn +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_cntdn IS + PORT ( + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + KEY : IN std_ulogic_vector(1 DOWNTO 0); -- KEY[1:0] + -- KEY[0] = rst_ni + -- KEY[1] = en_pi + GPO_1 : OUT std_ulogic_vector(5 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[3:0] = count_o + -- GPO_1[4] = tc_o + -- GPO_1[5] = clk_i + ); +END de1_cntdn; + +ARCHITECTURE structure OF de1_cntdn IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + +BEGIN + + -- connecting clock generator master clock of synchronous system + clk_i <= CLOCK_50; + GPO_1(5) <= clk_i; -- to measure clk signal + + -- connecting asynchronous system reset to digital system + rst_ni <= KEY(0); + + -- count enable input is high-active, KEY(1) ist low-aktive, therefore ... + -- ... if KEY1 is released, high signal is produced + en_pi <= KEY(1); + + + -- connecting device under test with peripheral elements + DUT : ENTITY work.cntdn(rtl) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- connecting count value to GPIO1 + GPO_1(3 DOWNTO 0) <= count_o; + GPO_1(4) <= tc_o; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_cntdnmodm_structure.vhd b/src/de1_cntdnmodm_structure.vhd new file mode 100644 index 0000000..d76c5f3 --- /dev/null +++ b/src/de1_cntdnmodm_structure.vhd @@ -0,0 +1,111 @@ +------------------------------------------------------------------------------- +-- Module : de1_cntdnmodm +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module cntdnmodm on a DE1 prototype board +-- connecting device under test (DUT) cntdnmodm +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_cntdnmodm IS + PORT ( + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + KEY : IN std_ulogic_vector(1 DOWNTO 0); -- KEY[1:0] + -- KEY[0] = rst_ni + -- KEY[1] = en_pi + GPO_1 : OUT std_ulogic_vector(7 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[3:0] = count_o + -- GPO_1[4] = tc_o + -- GPO_1[5] = clk_i + -- GPO_1[6] = tc_mod6_o + -- GPO_1[7] = tc_100hz_o + ); +END de1_cntdnmodm; + +ARCHITECTURE structure OF de1_cntdnmodm IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + + SIGNAL tc_mod6_o : std_ulogic; + SIGNAL tc_100hz_o : std_ulogic; + +BEGIN + + -- connecting clock generator master clock of synchronous system + clk_i <= CLOCK_50; + GPO_1(5) <= clk_i; -- to measure clk signal + + -- connecting asynchronous system reset to digital system + rst_ni <= KEY(0); + + -- count enable input is high-active, KEY(1) ist low-aktive, therefore ... + -- ... if KEY1 is released, high signal is produced + en_pi <= KEY(1); + + + -- connecting device under test with peripheral elements + DUT : ENTITY work.cntdnmodm + GENERIC MAP ( + n => 4, + m => 10) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- 3-bit modulo-6 down counter + mod6_count : ENTITY work.cntdnmodm + GENERIC MAP ( + n => 3, + m => 6) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => OPEN, + tc_o => tc_mod6_o); + + -- instantiate and parameterise the generics to + -- create a frequency of 100 Hz at its output signal tc_100hz_o + -- declare the necessary signals count_modxxx_o and tc_100hz_o + ----------------------------------------------------------------------------- +-- prescaler : cntdnmodm +-- GENERIC MAP ( +-- n => +-- m => ) +-- PORT MAP ( + ----------------------------------------------------------------------------- + + -- connecting count value to GPIO1 + GPO_1(3 DOWNTO 0) <= count_o; + GPO_1(4) <= tc_o; + GPO_1(6) <= tc_mod6_o; + GPO_1(7) <= tc_100hz_o; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_dac_rtl.vhd b/src/de1_dac_rtl.vhd new file mode 100644 index 0000000..c1c90bf --- /dev/null +++ b/src/de1_dac_rtl.vhd @@ -0,0 +1,109 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- PLL for 100 MHz speed +library altera_mf; +use altera_mf.all; + +entity de1_dac is + port ( CLOCK_50 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + KEY0 : in std_ulogic; + DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual + DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + POWER_ON : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs +end entity; + +architecture rtl of de1_dac is + + -- Altera PLL + component altpll + generic ( + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; +-- clk0_phase_shift : STRING; +-- compensate_clock : STRING; + inclk0_input_frequency : natural; +-- intended_device_family : STRING; +-- lpm_hint : STRING; +-- lpm_type : STRING; + operation_mode : string; + port_inclk0 : string; + port_clk0 : string + ); + port ( + clk : out std_logic_vector (5 downto 0); + inclk : in std_logic_vector (1 downto 0) + ); + end component; + + signal pll_inclk : std_logic_vector(1 downto 0); + signal pll_outclk : std_logic_vector(5 downto 0); + + signal clk,rst_n : std_ulogic; + signal cnt : unsigned(13 downto 0); + signal phase_inc : unsigned(9 downto 0); + signal dac_a_reg, dac_a_next, dac_b_reg : unsigned(13 downto 0); + +begin + + pll_i0 : altpll + generic map ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, +-- clk0_phase_shift => "0", +-- compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + operation_mode => "NORMAL", + port_inclk0 => "PORT_USED", + port_clk0 => "PORT_USED" + ) + port map ( + inclk => pll_inclk, + clk => pll_outclk + ); + + pll_inclk(0) <= CLOCK_50; + pll_inclk(1) <= '0'; + + clk <= pll_outclk(0); + rst_n <= '0' when KEY0 = '0' else '1' when rising_edge (clk); + LEDR <= SW; + + DAC_MODE <= '1'; --dual port + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + + phase_inc <= unsigned(SW(9 downto 1) & '0'); + + cnt <= (others => '0') when rst_n = '0' else cnt+phase_inc when rising_edge(clk); + + dac_a_next <= (others => '1') when cnt = 0 else (others => '0'); + dac_a_reg <= (others => '0') when rst_n = '0' else dac_a_next when falling_edge(clk); + dac_b_reg <= (others => '0') when rst_n = '0' else cnt when falling_edge(clk); + DAC_DA <= std_ulogic_vector(dac_a_reg); + DAC_DB <= std_ulogic_vector(dac_b_reg); + + -- ADC Section - switch off everything + ADC_CLK_A <= '0'; + ADC_CLK_B <= '0'; + ADC_OEB_A <= '1'; + ADC_OEB_B <= '1'; + POWER_ON <= '1'; + +end architecture rtl; diff --git a/src/de1_matlab_audio.vhd b/src/de1_matlab_audio.vhd new file mode 100644 index 0000000..4d7e613 --- /dev/null +++ b/src/de1_matlab_audio.vhd @@ -0,0 +1,126 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_matlab_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + SW: in std_ulogic_vector(9 downto 0); + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_logic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_matlab_audio is + + -- Matlab generated toplevel + component ml_audio is + port (clk : in std_logic; + rst_n : in std_logic; + clk_enable : in std_logic; + ce_out : out std_logic; + switches_i : in std_logic_vector(9 downto 0); + audio_i : in std_logic_vector(15 downto 0); + audio_o : out std_logic_vector(15 downto 0)); + end component; + + -- Wolfson AudioCodec Interface block + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data : std_logic_vector(15 downto 0); + signal adc_data, dac_data_reg : std_ulogic_vector(15 downto 0); + signal ml_audio_out_valid : std_ulogic; + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + ml_audio_i0 : ml_audio + port map ( + clk => clk, + rst_n => reset_n, + clk_enable => adc_valid, + ce_out => ml_audio_out_valid, + switches_i => std_logic_vector(SW), + audio_i => std_logic_vector(adc_data), + audio_o => dac_data); + + dac_data_reg <= std_ulogic_vector(dac_data) when rising_edge(clk) and ml_audio_out_valid = '1'; + + -- Wolfson Audio Codec + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data_reg, + dac_strobe_o => dac_strobe); + + LEDR <= SW; + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture diff --git a/src/de1_mux2to1_structure.vhd b/src/de1_mux2to1_structure.vhd new file mode 100644 index 0000000..33c1257 --- /dev/null +++ b/src/de1_mux2to1_structure.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Module : de1_mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add1 on a DE1 prototype board +-- connecting device under test (DUT) add1 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_mux2to1 IS + PORT ( + SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic -- LED Red[0] + ); +END de1_mux2to1; + +ARCHITECTURE structure OF de1_mux2to1 IS + + COMPONENT mux2to1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : mux2to1 + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + sel_i => SW(2), + y_o => LEDR); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_sta.vhd b/src/de1_sta.vhd new file mode 100644 index 0000000..91a93aa --- /dev/null +++ b/src/de1_sta.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity de1_sta is + port ( + CLOCK_50 : in std_ulogic; + x_i : in unsigned(7 downto 0); + y_o : out unsigned(x_i'range) + ); +end de1_sta; + +architecture rtl of de1_sta is + +signal a,b,c,d : unsigned(x_i'range); +signal sum : unsigned(x_i'range); +signal clk : std_ulogic; + +begin + +clk <= CLOCK_50; + +sum <= a + b + c + d; + +y_o <= sum when rising_edge(clk); + +a <= x_i when rising_edge(clk); +b <= a when rising_edge(clk); +c <= b when rising_edge(clk); +d <= c when rising_edge(clk); + +end architecture; diff --git a/src/de1_tone.vhd b/src/de1_tone.vhd new file mode 100644 index 0000000..eff30f9 --- /dev/null +++ b/src/de1_tone.vhd @@ -0,0 +1,119 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_tone is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_logic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_tone is + + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + component tone is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + switches_i : in std_ulogic_vector(9 downto 0); + dv_i : in std_ulogic; + audio_i : in std_ulogic_vector(15 downto 0); + audio_o : out std_ulogic_vector(15 downto 0)); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data, + dac_strobe_o => dac_strobe); + + tone_i0 : tone + port map ( + clk => clk, + rst_n => reset_n, + dv_i => adc_valid, + audio_i => adc_data, + audio_o => dac_data, + switches_i => SW); + + LEDR(9 downto 0) <= SW; + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture + + diff --git a/src/e_falling_edge_detector.vhd b/src/e_falling_edge_detector.vhd new file mode 100644 index 0000000..db0cb16 --- /dev/null +++ b/src/e_falling_edge_detector.vhd @@ -0,0 +1,34 @@ +------------------------------------------------------------------------------- +-- Module : falling_edge_detector +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: detects a falling edge of input signal x_i +-- and produces a high-active signal for one clock period at +-- output fall_o +-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--| +-- x_i -----|___________________________________|----------- +-- fall_o ________|-----|______________________________________ +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY falling_edge_detector IS + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + x_i : IN std_ulogic; + fall_o : OUT std_ulogic + ); +END falling_edge_detector; + + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/fsgen.vhd b/src/fsgen.vhd new file mode 100644 index 0000000..e15deca --- /dev/null +++ b/src/fsgen.vhd @@ -0,0 +1,56 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Frame Sync Generator +-- The framesync is active for one bitclock cycle + +entity fsgen is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_falling_edge_en_i : in std_ulogic; + fs_o : out std_ulogic); +end; + +architecture rtl of fsgen is + constant max_count : integer := 127; + signal counter : integer range 0 to max_count; +begin + + fs_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + counter <= 0; + fs_o <= '0'; + elsif rising_edge(clk_i) then + if bclk_falling_edge_en_i = '1' then + fs_o <= '0'; + if counter = max_count then + counter <= 0; + fs_o <= '1'; + else + counter <= counter + 1; + end if; + end if; + end if; + end process fs_cnt_p; + +end; -- architecture + + diff --git a/src/i2c.vhd b/src/i2c.vhd new file mode 100644 index 0000000..f60cdbe --- /dev/null +++ b/src/i2c.vhd @@ -0,0 +1,245 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- I2C or 2-Wire Bus +-- To start a transaction, pull the data line to 'L' while the clock is still 'H' +-- 7 Bits Address +-- 1 Bit R/W (0 = Write, 1 = Read) +-- 1 Bit ACK (from Slave 0 if o.k.) +-- 8 Bits Data 15..8 +-- 1 Bit Ack from slave (0 if o.k.) +-- 8 Bits Data 7..0 +-- 1 Bit Ack from slave (0 if o.k.) + + +entity i2c is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_i: in std_ulogic; + data_i: in std_ulogic_vector(23 downto 0); + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + busy_o: out std_ulogic + ); +end; + +architecture rtl of i2c is + + -- Clock divider section + constant fd_c : integer := 50000000/20000/2; -- 50 MHz system clock, 20 kHz I2C clock + signal clk_cnt : integer range 0 to fd_c; + signal clk_cnt_reset, clk_cnt_done : std_ulogic; + + -- i2c data register index + signal idx : integer range 0 to 27; + signal idx_inc : std_ulogic; + signal idx_reset : std_ulogic; + + -- i2c registers with and without data for the acknowledgment section + -- In cycle 8, 17 and 26 there is an i2c acknowledgement cycle where the master + -- drives Z and the slave will drive "0" when everything is o.k. + -- The input data from the interface is without these acknowledgement bits + signal load_i2c_reg_without_ack : std_ulogic; + signal i2c_reg_without_ack : std_ulogic_vector(23 downto 0); + signal i2c_reg_with_ack : std_ulogic_vector(0 to 27); + + -- Statemachine + type state_t is (idle_s, start_s, data_hold_s, data_s, clock_high_s, stop_s); + signal state, next_state : state_t; + + -- Selection for the i2c output data + type i2c_dat_sel_t is (sel_old, sel_reg, sel_one, sel_zero); + signal i2c_dat_sel : i2c_dat_sel_t; + + type i2c_clk_sel_t is (sel_old, sel_one, sel_zero); + signal i2c_clk_sel : i2c_clk_sel_t; + + signal i2c_clk : std_ulogic; + signal i2c_clk_new : std_ulogic; + signal i2c_dat : std_ulogic; + signal i2c_dat_new : std_ulogic; + +begin + + -- i2c register with ack build from i2c without ack + -- i2c data is transmitted msb first, so bus direction is changed also + i2c_reg_with_ack(0 to 7) <= i2c_reg_without_ack(23 downto 16); + i2c_reg_with_ack(8) <= '1'; + i2c_reg_with_ack(9 to 16) <= i2c_reg_without_ack(15 downto 8); + i2c_reg_with_ack(17) <= '1'; + i2c_reg_with_ack(18 to 25) <= i2c_reg_without_ack(7 downto 0); + i2c_reg_with_ack(26) <= '1'; + i2c_reg_with_ack(27) <= '0'; + + -- This process counts the clocks for reducing the clock speed + -- of the i2c clock + clk_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + clk_cnt <= 0; + elsif rising_edge(clk_i) then + if clk_cnt < fd_c then + clk_cnt <= clk_cnt + 1; + end if; + if clk_cnt_reset = '1' then + clk_cnt <= 0; + end if; + end if; + end process clk_cnt_p; + + clk_cnt_done <= '1' when clk_cnt = fd_c else '0'; + + -- This is the index for the i2c register. + i2c_idx_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + elsif rising_edge(clk_i) then + if idx_inc = '1' and idx < 27 then + idx <= idx + 1; + end if; + if idx_reset = '1' then + idx <= 0; + end if; + end if; + end process i2c_idx_p; + + -- This are the registered outputs for the i2c clock and data + i2c_out_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + i2c_clk <= '1'; + i2c_dat <= '1'; + elsif rising_edge(clk_i) then + i2c_dat <= i2c_dat_new; + i2c_clk <= i2c_clk_new; + end if; + end process i2c_out_p; + + -- The i2c register without ack data + i2c_data_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + i2c_reg_without_ack <= (others => '0'); + elsif rising_edge(clk_i) then + if load_i2c_reg_without_ack = '1' then + i2c_reg_without_ack <= data_i; + end if; + end if; + end process i2c_data_p; + + -- i2c data selection process + i2c_dat_sel_p : process(i2c_dat_sel, i2c_reg_with_ack, i2c_dat, idx) + begin + case i2c_dat_sel is + when sel_old => i2c_dat_new <= i2c_dat; + when sel_reg => i2c_dat_new <= i2c_reg_with_ack(idx); + when sel_one => i2c_dat_new <= '1'; + when sel_zero => i2c_dat_new <= '0'; + when others => i2c_dat_new <= '0'; + end case; + end process i2c_dat_sel_p; + + -- i2c clock selection process + i2c_clk_sel_p : process(i2c_clk, i2c_clk_sel) + begin + case i2c_clk_sel is + when sel_old => i2c_clk_new <= i2c_clk; + when sel_one => i2c_clk_new <= '1'; + when sel_zero => i2c_clk_new <= '0'; + when others => i2c_clk_new <= '0'; + end case; + end process i2c_clk_sel_p; + + -- Sequential process for the statemachine + statem_seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + state <= idle_s; + elsif rising_edge(clk_i) then + state <= next_state; + end if; + end process statem_seq_p; + + statem_comb_p: process(state, load_i, idx, clk_cnt_done) + begin + load_i2c_reg_without_ack<= '0'; + idx_inc <= '0'; + idx_reset <= '0'; + clk_cnt_reset <= '0'; + busy_o <= '1'; + i2c_dat_sel <= sel_old; + i2c_clk_sel <= sel_old; + next_state <= state; + case state is + when idle_s => + busy_o <= '0'; + i2c_clk_sel <= sel_one; + i2c_dat_sel <= sel_one; + if load_i = '1' then + load_i2c_reg_without_ack <= '1'; + clk_cnt_reset <= '1'; + idx_reset <= '1'; + next_state <= start_s; + i2c_dat_sel <= sel_zero; + end if; + when start_s => + if clk_cnt_done = '1' then + next_state <= data_hold_s; + clk_cnt_reset <= '1'; + i2c_clk_sel <= sel_zero; + end if; + when data_hold_s => + next_state <= data_s; + i2c_dat_sel <= sel_reg; + when data_s => + if clk_cnt_done = '1' then + next_state <= clock_high_s; + i2c_clk_sel <= sel_one; + clk_cnt_reset <= '1'; + end if; + when clock_high_s => + if clk_cnt_done = '1' then + if idx = 27 then -- last bit transmitted + i2c_dat_sel <= sel_one; + next_state <= stop_s; + else + idx_inc <= '1'; + i2c_clk_sel <= sel_zero; + next_state <= data_hold_s; + end if; + clk_cnt_reset <= '1'; + end if; + when stop_s => + if clk_cnt_done = '1' then + next_state <= idle_s; + end if; + when others => + next_state <= idle_s; + end case; + end process statem_comb_p; + + i2c_clk_o <= i2c_clk; + i2c_dat_o <= i2c_dat; + +end; -- architecture + + diff --git a/src/i2c_sub.vhd b/src/i2c_sub.vhd new file mode 100644 index 0000000..e71ff39 --- /dev/null +++ b/src/i2c_sub.vhd @@ -0,0 +1,79 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_sub is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + i2c_clk_o: out std_ulogic); +end; + +architecture struct of i2c_sub is + +component i2c is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_i: in std_ulogic; + data_i: in std_ulogic_vector(23 downto 0); + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + busy_o: out std_ulogic + ); +end component; + +component i2c_write is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_o: out std_ulogic; + data_o: out std_ulogic_vector(23 downto 0); + busy_i: in std_ulogic); +end component; + + signal load, busy : std_ulogic; + signal data : std_ulogic_vector(23 downto 0); + +begin + + i2c_i0 : i2c + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_i => load, + data_i => data, + i2c_clk_o => i2c_clk_o, + i2c_dat_o => i2c_dat_o, + i2c_dat_i => i2c_dat_i, + busy_o => busy); + + i2_write_i0 : i2c_write + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_o => load, + data_o => data, + busy_i => busy); + +end; -- architecture + + diff --git a/src/i2c_write.vhd b/src/i2c_write.vhd new file mode 100644 index 0000000..338a3a7 --- /dev/null +++ b/src/i2c_write.vhd @@ -0,0 +1,98 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_write is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_o: out std_ulogic; + data_o: out std_ulogic_vector(23 downto 0); + busy_i: in std_ulogic); +end; + +architecture rtl of i2c_write is + constant num_regs_c : integer := 12; + type state_t is (start_s, wait_s, done_s); + signal state, next_state : state_t; + signal counter : integer range 0 to num_regs_c-1; + signal counter_enable : std_ulogic; + type data_array_t is array(0 to num_regs_c-1) of std_ulogic_vector(23 downto 0); + + constant data_array : data_array_t := ( + X"341200", -- Set Inactive + X"341E00", -- Reset the Device + X"34001A", -- Left Line In / Mute off / Volume + X"34021A", -- Right Line In + X"34046F", -- Headphone Left + X"34066F", -- Headphone Right + X"340815", -- Analog path control (MIC to ADC, DAC to output, MIC Boost) + X"340A00", -- Digital path control + X"340C61", -- Power Down Control (Everything switched on) + X"340E13", -- Digital Audio Interface Format (Slave Mode, DSP Mode, 16 Bit) + X"341000", -- Sampling Control (48 kHz Sampling frequency, Normal Mode) + X"341201"); -- Active Control (Activate) + +begin + + seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + state <= start_s; + counter <= 0; + elsif rising_edge(clk_i) then + state <= next_state; + if counter_enable = '1' then + if counter < num_regs_c - 1 then + counter <= counter + 1; + else + counter <= 0; + end if; + end if; + end if; + end process seq_p; + + data_o <= data_array(counter); + + process(state, counter, busy_i) + begin + load_o <= '0'; + counter_enable <= '0'; + next_state <= state; + case state is + when start_s => + load_o <= '1'; + next_state <= wait_s; + when wait_s => + if busy_i = '0' then + if counter = num_regs_c-1 then + next_state <= done_s; + --counter_enable <= '1'; + else + next_state <= start_s; + counter_enable <= '1'; + end if; + end if; + when others => + next_state <= state; + end case; + end process; + +end; -- architecture + + diff --git a/src/invgate_equation.vhd b/src/invgate_equation.vhd new file mode 100644 index 0000000..69e920e --- /dev/null +++ b/src/invgate_equation.vhd @@ -0,0 +1,34 @@ +-------------------------------------------------------------------------------
+-- Module : invgate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Inverter Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY invgate IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ y_o : OUT std_ulogic -- data output y
+ );
+END invgate;
+
+ARCHITECTURE equation OF invgate IS
+
+BEGIN
+
+ y_o <= NOT a_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mclk.vhd b/src/mclk.vhd new file mode 100644 index 0000000..5da923d --- /dev/null +++ b/src/mclk.vhd @@ -0,0 +1,48 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Master Clock Generator +-- Generate 12.5 MHz from 50 MHz by dividing by 4 +-- Audio Codec expects 12.288 MHz, so we are slightly higher + +entity mclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + mclk_o : out std_ulogic); +end; + +architecture rtl of mclk is + signal mclk : unsigned(1 downto 0); +begin + + mclk_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + mclk <= to_unsigned(0, mclk'length); + elsif rising_edge(clk_i) then + mclk <= mclk + 1; + end if; + end process mclk_p; + + mclk_o <= mclk(1); + +end; -- architecture + + diff --git a/src/memory.vhd b/src/memory.vhd new file mode 100644 index 0000000..e50d687 --- /dev/null +++ b/src/memory.vhd @@ -0,0 +1,54 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This VHDL memory description will result in FPGA memory usage. +-- The EPC2C20 series provides a total of 52 M4K memory blocks +-- Each M4K memory block contains 4608 Bits. The following configurations are supported: +-- 4K 1, 2K 2, 1K 4, 512 8, 512 9, 256 16, 256 18 +-- The maximum is therefore 52 x 256 = 13312 samples. + +entity memory is + port ( + clk_i : in std_ulogic; + we_i : in std_ulogic; + waddr_i : in unsigned(12 downto 0); + raddr_i : in unsigned(12 downto 0); + wdata_i : in std_ulogic_vector(15 downto 0); + rdata_o : out std_ulogic_vector(15 downto 0) + ); +end; + +architecture rtl of memory is + type ram_t is array(0 to 2 ** 13 - 1) of std_ulogic_vector(15 downto 0); + signal ram : ram_t; +begin + + mem_p : process(clk_i) + begin + if rising_edge(clk_i) then + if we_i = '1' then + ram(to_integer(waddr_i)) <= wdata_i; + end if; + rdata_o <= ram(to_integer(raddr_i)); + end if; + end process mem_p; + +end; -- architecture + + diff --git a/src/mux2to1_equation.vhd b/src/mux2to1_equation.vhd new file mode 100644 index 0000000..0fddb6a --- /dev/null +++ b/src/mux2to1_equation.vhd @@ -0,0 +1,40 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by boolean equation
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE equation OF mux2to1 IS
+
+BEGIN
+
+ y_o <= (sel_i AND a_i) OR (NOT sel_i AND b_i);
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_rtl.vhd b/src/mux2to1_rtl.vhd new file mode 100644 index 0000000..c6447dd --- /dev/null +++ b/src/mux2to1_rtl.vhd @@ -0,0 +1,42 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by a conditional signal assignment
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE rtl OF mux2to1 IS
+
+BEGIN
+
+ y_o <= a_i WHEN sel_i = '1' ELSE
+ b_i WHEN sel_i = '0' ELSE
+ 'X';
+
+END rtl;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_structure.vhd b/src/mux2to1_structure.vhd new file mode 100644 index 0000000..3ff0c97 --- /dev/null +++ b/src/mux2to1_structure.vhd @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled as structure of basic logic gates
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE structure OF mux2to1 IS
+
+ COMPONENT invgate
+ PORT (
+ a_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ COMPONENT and2gate
+ PORT (
+ a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ COMPONENT or2gate
+ PORT (
+ a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ SIGNAL p0, p1 : std_ulogic;
+ SIGNAL p2 : std_ulogic;
+
+BEGIN
+
+ inv_gate_1 : invgate
+ PORT MAP (
+ a_i => sel_i,
+ y_o => p2);
+
+ and2_gate_1 : and2gate
+ PORT MAP (
+ a_i => a_i,
+ b_i => sel_i,
+ y_o => p0);
+
+ and2_gate_2 : and2gate
+ PORT MAP (
+ a_i => b_i,
+ b_i => p2,
+ y_o => p1);
+
+ or2_gate_1 : or2gate
+ PORT MAP (
+ a_i => p0,
+ b_i => p1,
+ y_o => y_o);
+
+-- inv_gate_1 : invgate PORT MAP (sel_i, p2);
+
+-- and2_gate_1 : and2gate PORT MAP (a_i, sel_i, p0);
+
+-- and2_gate_2 : and2gate PORT MAP (b_i, p2, p1);
+
+-- or2_gate_1 : or2gate PORT MAP (p0, p1, y_o);
+
+END structure;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_structure_errors.vhd b/src/mux2to1_structure_errors.vhd new file mode 100644 index 0000000..0b33968 --- /dev/null +++ b/src/mux2to1_structure_errors.vhd @@ -0,0 +1,79 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled as structure of basic logic gates
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ sel_i : IN std_ulogic;
+-- y_o : OUT std_ulogic; -- kein ; nach letztem Signal
+ y_o : OUT std_ulogic
+ );
+END mux21;
+
+
+ARCHITECTURE structure OF mux2to1 IS
+
+ COMPONENT invgate
+ PORT (
+ a_i : IN std_ulogic;
+ y_o : OUT std_ulogic);
+ END COMPONENT;
+
+ COMPONENT or2gate
+ PORT (
+ a_i : IN std_ulogic;
+ b_i : IN std_ulogic;
+ y_o : std_ulogic);
+ END COMPONENT;
+
+ SIGNAL p1 : std_ulogic;
+ SIGNAL p2 : std_ulogic;
+ SIGNAL p3 : std_ulogic;
+
+BEGIN
+
+ inv_gate_1 : invgate
+ PORT MAP (
+ a_i => sel_i,
+ y_o <= p2);
+
+
+ and2_gate_1 : and2gate
+ PORT MAP (
+ a_i => a_i,
+ b_i => p2
+ y_o => p0);
+
+ and2_gate_2 : and2gate
+ PORT MAP (
+ a_i => b_i,
+ b_i => sel_i,
+ y_o => p1);
+
+ or2_gate_1 : or2gate
+ PORT MAP (
+ a_i => p0,
+ b_i => p1,
+ y_o => p3);
+
+
+END struct
+
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/mux2to1_truthtable.vhd b/src/mux2to1_truthtable.vhd new file mode 100644 index 0000000..ff84c61 --- /dev/null +++ b/src/mux2to1_truthtable.vhd @@ -0,0 +1,54 @@ +-------------------------------------------------------------------------------
+-- Module : mux2to1
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+-- function modelled by a truth table
+-- sel = '1': a -> y
+-- sel = '0': b -> y
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ sel_i : IN std_ulogic; -- select which input is connected to y
+ -- sel = '1': a -> y
+ -- sel = '0': b -> y
+ y_o : OUT std_ulogic -- data output y
+ );
+END mux2to1;
+
+ARCHITECTURE truthtable OF mux2to1 IS
+
+ SIGNAL inputs_s : std_ulogic_vector(2 DOWNTO 0); -- temp input vector
+
+BEGIN
+
+ inputs_s <= (sel_i, b_i, a_i); -- concatenate single signals to a vector
+
+ tt : WITH inputs_s SELECT -- truthtable
+ y_o <=
+ '0' WHEN "000",
+ '0' WHEN "001",
+ '1' WHEN "010",
+ '1' WHEN "011",
+ '0' WHEN "100",
+ '1' WHEN "101",
+ '0' WHEN "110",
+ '1' WHEN "111",
+ 'X' WHEN OTHERS;
+
+END truthtable;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
diff --git a/src/or2gate_equation.vhd b/src/or2gate_equation.vhd new file mode 100644 index 0000000..13795fb --- /dev/null +++ b/src/or2gate_equation.vhd @@ -0,0 +1,18 @@ +-------------------------------------------------------------------------------
+-- Module : or2gate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-input OR Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
diff --git a/src/play_rtl.vhd b/src/play_rtl.vhd new file mode 100644 index 0000000..8452236 --- /dev/null +++ b/src/play_rtl.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------ +-- module : play +------------------------------------------------------------------ +-- author : Friedrich Beckmann +-- company : university of applied sciences augsburg +------------------------------------------------------------------ +-- description: Statemachine for LED game +-- +------------------------------------------------------------------ +-- revisions : 0.1 - +------------------------------------------------------------------ + +-- 5 LED outputs +-- One one-second enable input +-- KEY input with preceding rising_edge detector + +-- step LED4 LED3 LED2 LED1 LED0 +-- 1 x - - - - +-- 2 - x - - - +-- 3 - - x - - +-- 4 - - - x - +-- 5 - - - - x +-- 6 x - - - - +-- ... this pattern continues +-- If LED2 is on and KEY is pressed then the pattern continues as follows +-- 1 x - - - - +-- 2 - - - - x +-- ... this pattern continues until +-- KEY is pressed again. Then the previous pattern restarts from LED 2 + +library ieee; +use ieee.std_logic_1164.all; + +entity play is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + onesec_i : in std_ulogic; + key_i : in std_ulogic; + led_o : out std_ulogic_vector(4 downto 0)); +end play; + +architecture rtl of play is + + type state_t is (start_s,one_s,chance_s,four_s,last_s,hit0_s,hit1_s); + signal current_state,next_state : state_t; + +begin + + current_state <= start_s when rst_n = '0' else next_state when rising_edge(clk); + + next_p : process(current_state, onesec_i, key_i) + begin + next_state <= current_state; + led_o <= "00000"; + case current_state is + when start_s => + led_o <= "10000"; + if onesec_i = '1' then + next_state <= one_s; + end if; + when one_s => + led_o <= "01000"; + if onesec_i = '1' then + next_state <= chance_s; + end if; + when chance_s => + led_o <= "00100"; + if key_i = '1' then + next_state <= hit0_s; + elsif onesec_i = '1' then + next_state <= four_s; + end if; + when four_s => + led_o <= "00010"; + if onesec_i = '1' then + next_state <= last_s; + end if; + when last_s => + led_o <= "00001"; + if onesec_i = '1' then + next_state <= start_s; + end if; + when hit0_s => + led_o <= "10000"; + if key_i = '1' then + next_state <= chance_s; + elsif onesec_i = '1' then + next_state <= hit1_s; + end if; + when hit1_s => + led_o <= "00001"; + if key_i = '1' then + next_state <= chance_s; + elsif onesec_i = '1' then + next_state <= hit0_s; + end if; + when others => null; + end case; + end process; + +end architecture rtl; diff --git a/src/ringbuf.vhd b/src/ringbuf.vhd new file mode 100644 index 0000000..7c45815 --- /dev/null +++ b/src/ringbuf.vhd @@ -0,0 +1,74 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Ring Buffer stores samples in a circular buffer +-- The read buffer pointer is one buffer entry ahead +-- of the write buffer pointer. + +entity ringbuf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0)); +end; + +architecture rtl of ringbuf is + +component memory is + port ( + clk_i : in std_ulogic; + we_i : in std_ulogic; + waddr_i : in unsigned(12 downto 0); + raddr_i : in unsigned(12 downto 0); + wdata_i : in std_ulogic_vector(15 downto 0); + rdata_o : out std_ulogic_vector(15 downto 0) + ); +end component; + + signal raddr, waddr : unsigned(12 downto 0); + +begin + + mem_i0 : memory + port map ( + clk_i => clk_i, + we_i => en_i, + raddr_i => raddr, + waddr_i => waddr, + rdata_o => data_o, + wdata_i => data_i); + + buffer_pointer_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + waddr <= to_unsigned(0, 13); + raddr <= to_unsigned(1, 13); + elsif rising_edge(clk_i) then + if en_i = '1' then + raddr <= raddr + 1; + waddr <= waddr + 1; + end if; + end if; + end process buffer_pointer_p; + +end; -- architecture + + diff --git a/src/t_cntdn.vhd b/src/t_cntdn.vhd new file mode 100644 index 0000000..42888c6 --- /dev/null +++ b/src/t_cntdn.vhd @@ -0,0 +1,123 @@ +------------------------------------------------------------------------------- +-- Module : t_cntdn +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "cntdn" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY t_cntdn IS +END t_cntdn; + +ARCHITECTURE tbench OF t_cntdn IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + DUT : cntdn + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- clock generation + clock_proc : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset, always necessary at the beginning of a simulation + -- initial reset, always necessary at the beginning of a simulation + ----------------------------------------------------------------------------- + -- Following a verification plan: + -- ------------------------------ + -- 1. t = 0 ns: activate asynchronous reset + -- 2. t = 10 ns: deactivate asynchronous reset + ----------------------------------------------------------------------------- + reset : rst_ni <= '0', '1' AFTER period; + + stimuli_p : PROCESS + + BEGIN + + --------------------------------------------------------------------------- + -- ... continuing with the verification plan: + --------------------------------------------------------------------------- + WAIT UNTIL rising_edge(rst_ni); -- wait for reset + -- ... is deactivated + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 2. activate enable + -- 3. Wait for a full counting cycle + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- 4. After another five periods: Deactivate Enable + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 5. After another three periods: Activate Enable + -- 6. Simulate another complete counting cycle + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 7. Simulate until tc_o = 1 again + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + + clken_p <= false; -- switch clock generator off + + WAIT; -- suspend proces + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_cntdnmodm.vhd b/src/t_cntdnmodm.vhd new file mode 100644 index 0000000..5b3b9e3 --- /dev/null +++ b/src/t_cntdnmodm.vhd @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------- +-- Module : t_cntdnmodm +------------------------------------------------------------------------------- +-- Author : <johann.faerber@hs-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2013 <johann.faerber@hs-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "cntdnmodm" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY t_cntdnmodm IS +END t_cntdnmodm; + +ARCHITECTURE tbench OF t_cntdnmodm IS + + COMPONENT cntdnmodm + GENERIC ( + n : natural; + m : natural); + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(n-1 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + -- component generics + CONSTANT n : natural := 4; + CONSTANT m : natural := 10; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(n-1 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + + SIGNAL count_mod6_o : std_ulogic_vector(2 DOWNTO 0); + SIGNAL tc_mod6_o : std_ulogic; + + SIGNAL count_mod500e3_o : std_ulogic_vector(18 DOWNTO 0); + SIGNAL tc_100hz_o : std_ulogic; + + + -- definition of a clock period + CONSTANT period : time := 20 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + +BEGIN -- tbench + + -- component instantiation + MUV : cntdnmodm + GENERIC MAP ( + n => n, + m => m) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + mod6_count : cntdnmodm + GENERIC MAP ( + n => 3, + m => 6) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_mod6_o, + tc_o => tc_mod6_o); + + -- instantiate and parameterise the generics to + -- create a frequency of 100 Hz at its output signal tc_100hz_o + -- declare the necessary signals count_modxxx_o and tc_100hz_o + ----------------------------------------------------------------------------- +-- prescaler : cntdnmodm +-- GENERIC MAP ( +-- n => +-- m => ) +-- PORT MAP ( + ----------------------------------------------------------------------------- + + + -- clock generation + clock_p : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset + reset : rst_ni <= '1', '0' AFTER period, + '1' AFTER 2 * period; + + -- process for stimuli generation + stimuli_p : PROCESS + + BEGIN + + WAIT UNTIL rising_edge(rst_ni); -- wait for reset + + en_pi <= '1'; -- activate counter + + + -- wait for a period of tc_o ---------------------------------------------- + WAIT UNTIL rising_edge(tc_o); + WAIT UNTIL falling_edge(tc_o); + + WAIT UNTIL count_o = X"5"; + + en_pi <= '0'; -- stop counter ... + WAIT FOR 3* period; -- ... for 3 periods + + en_pi <= '1'; -- activate counter + + -- wait for a period of tc_mod6_o ----------------------------------------- + WAIT UNTIL rising_edge(tc_mod6_o); + WAIT UNTIL falling_edge(tc_mod6_o); + --------------------------------------------------------------------------- + + + -- wait for a period of tc_100hz_o ---------------------------------------- + + --------------------------------------------------------------------------- + + + -- wait for a period of tc_100hz_o ---------------------------------------- + + --------------------------------------------------------------------------- + + + clken_p <= false; -- switch clock generator off + + WAIT; + END PROCESS; + + + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_de1_audio.vhd b/src/t_de1_audio.vhd new file mode 100644 index 0000000..bfa0f1f --- /dev/null +++ b/src/t_de1_audio.vhd @@ -0,0 +1,88 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity t_de1_audio is +end; + +architecture tbench of t_de1_audio is + +component de1_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_ulogic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0) + ); +end component; + + signal clk, reset_n : std_ulogic; + signal ledr : std_ulogic_vector(9 downto 0); + signal i2c_clk, i2c_dat : std_ulogic; + signal key0 : std_ulogic; + + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + + signal simrun : boolean := true; + +begin + + de1_audio_i0 : de1_audio + port map ( + CLOCK_50 => clk, + KEY0 => reset_n, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + LEDR => ledr); + + clock_p : process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + if not simrun then + wait; + end if; + end process clock_p; + + simrun <= false after 1 ms; + + reset_p : process + begin + reset_n <= '0'; + wait for 15 us; + reset_n <= '1'; + wait; + end process reset_p; + + aud_adcdat <= '1'; + +end; -- architecture diff --git a/src/t_de1_play.vhd b/src/t_de1_play.vhd new file mode 100644 index 0000000..8a2b739 --- /dev/null +++ b/src/t_de1_play.vhd @@ -0,0 +1,100 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity t_de1_play is +end t_de1_play; + +architecture tbench of t_de1_play is + +component de1_play is + port ( + CLOCK_50 : in std_ulogic; -- 50 mhz clock + KEY : in std_ulogic_vector(1 downto 0); -- key(1..0) + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_logic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0) + LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0) + ); +end component; + + -- definition of a clock period + constant period : time := 10 ns; + -- switch for clock generator + signal clken_p : boolean := true; + + + signal clk_i : std_ulogic; + signal rst_ni : std_ulogic; + signal key : std_ulogic; + signal ledr : std_ulogic_vector(4 downto 0); + + signal i2c_clk, i2c_dat : std_ulogic; + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + signal phase : real := 0.0; + signal test_tone : real; + signal test_tone_quantized : signed(15 downto 0); + signal bit_count : integer range 0 to 31; + +begin + + -- clock generation + clock_proc : process + begin + while clken_p loop + clk_i <= '0'; wait for period/2; + clk_i <= '1'; wait for period/2; + end loop; + wait; + end process; + + -- initial reset, always necessary at the beginning of a simulation + reset : rst_ni <= '0', '1' AFTER period; + + stimuli_p : process + begin + key <= '1'; + wait until rst_ni = '1'; + wait for 20*period; + key <= '0'; + wait for 10*period; + key <= '1'; + wait for 30*period; + clken_p <= false; + wait; + end process stimuli_p; + + + de1_play_i0 : de1_play + port map ( + CLOCK_50 => clk_i, + KEY(0) => rst_ni, + KEY(1) => key, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + LEDR => ledr); + + aud_adcdat <= test_tone_quantized(bit_count mod 16); + + -- Test tone generator for simulating the ADC from the audio codec + phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck); + test_tone <= sin(2*3.14*phase); + test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16); + bit_count <= 31 when falling_edge(aud_daclrck) else + 0 when bit_count = 0 else + bit_count - 1 when falling_edge(aud_bclk); + +end tbench; diff --git a/src/t_de1_tone.vhd b/src/t_de1_tone.vhd new file mode 100644 index 0000000..37d9e6b --- /dev/null +++ b/src/t_de1_tone.vhd @@ -0,0 +1,108 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity t_de1_tone is +end; + +architecture tbench of t_de1_tone is + + component de1_tone is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_ulogic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + LEDR : out std_ulogic_vector(9 downto 0) + ); + end component; + + signal clk, reset_n : std_ulogic; + signal ledr : std_ulogic_vector(9 downto 0); + signal i2c_clk, i2c_dat : std_ulogic; + signal key0 : std_ulogic; + + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + + signal simrun : boolean := true; + + signal phase : real := 0.0; + signal test_tone : real; + signal test_tone_quantized : signed(15 downto 0); + signal bit_count : integer range 0 to 31; + signal switches : std_ulogic_vector(9 downto 0); + +begin + + de1_tone_i0 : de1_tone + port map ( + CLOCK_50 => clk, + KEY0 => reset_n, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + SW => switches, + LEDR => ledr); + + clock_p : process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + if not simrun then + wait; + end if; + end process clock_p; + + simrun <= false after 5 ms; + + reset_p : process + begin + reset_n <= '0'; + wait for 15 us; + reset_n <= '1'; + wait; + end process reset_p; + + aud_adcdat <= test_tone_quantized(bit_count mod 16); + + -- Test tone generator for simulating the ADC from the audio codec + phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck); + test_tone <= sin(2*3.14*phase); + test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16); + bit_count <= 31 when falling_edge(aud_daclrck) else + 0 when bit_count = 0 else + bit_count - 1 when falling_edge(aud_bclk); + + + +end; -- architecture diff --git a/src/t_falling_edge_detector.vhd b/src/t_falling_edge_detector.vhd new file mode 100644 index 0000000..9fda089 --- /dev/null +++ b/src/t_falling_edge_detector.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- Module : t_falling_edge_detector +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "falling_edge_detector" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_falling_edge_detector IS +END t_falling_edge_detector; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_falling_edge_detector IS + + COMPONENT falling_edge_detector + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + x_i : IN std_ulogic; + fall_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL x_i : std_ulogic; + SIGNAL fall_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : falling_edge_detector + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + x_i => x_i, + fall_o => fall_o); + + -- clock generation + clock_p : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset, always necessary at the beginning of a simulation + reset : rst_ni <= '0', '1' AFTER period; + + + stimuli_p : PROCESS + BEGIN + + WAIT UNTIL rst_ni = '1'; -- wait until asynchronous reset ... + -- ... is deactivated + --------------------------------------------------------------------------- + + -- create a low-active pulse over a no. of clock periods + --------------------------------------------------------------------------- + x_i <= '1'; -- assign a '1' to x_i + WAIT FOR period; + + x_i <= '0'; -- set input to '0' ... + WAIT UNTIL rising_edge(clk_i); + WAIT UNTIL falling_edge(clk_i); + -- Observer: check, if fall_o is assigned to '1' for one clock period + ASSERT fall_o = '1' REPORT "Error: Expected fall_o = '1' !" SEVERITY failure; + WAIT UNTIL falling_edge(clk_i); + ASSERT fall_o = '0' REPORT "Error: Expected fall_o = '0' !" SEVERITY failure; + WAIT FOR 6 * period; -- ... for a no. of periods + + x_i <= '1'; -- assign a '1' to form a + WAIT FOR 3 * period; -- low active input pulse + --------------------------------------------------------------------------- + + + -- add another low-active input pulse here ... + + + + + + + + + + clken_p <= false; -- switch clock generator off + + WAIT; -- suspend proces + END PROCESS; + + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_mux2to1.vhd b/src/t_mux2to1.vhd new file mode 100644 index 0000000..4d4d118 --- /dev/null +++ b/src/t_mux2to1.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- Module : t_mux2to1 +------------------------------------------------------------------------------- +-- Author : <haf@fh-augsburg.de> +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 <haf@fh-augsburg.de> +------------------------------------------------------------------------------- +-- Description: Testbench for design "mux2to1" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_mux2to1 IS +END t_mux2to1; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_mux2to1 IS + + COMPONENT mux2to1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + + -- component ports + SIGNAL a_i : std_ulogic; + SIGNAL b_i : std_ulogic; + SIGNAL sel_i : std_ulogic; + SIGNAL y_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : mux2to1 + PORT MAP ( + a_i => a_i, + b_i => b_i, + sel_i => sel_i, + y_o => y_o); + + stimuli_p : PROCESS + + BEGIN + a_i <= '0'; -- set a value to input a_i + b_i <= '0'; -- set a value to input b_i + sel_i <= '0'; -- set a value to input ci_i + WAIT FOR period; -- values are assigned here + + a_i <= '1'; -- change value of a_i + WAIT FOR period; + + a_i <= '0'; -- change value of a_i + b_i <= '1'; -- change value of b_i + WAIT FOR period; + + + -- add the missing stimuli here ... + + + + WAIT; + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/tone_rtl.vhd b/src/tone_rtl.vhd new file mode 100644 index 0000000..815ebb8 --- /dev/null +++ b/src/tone_rtl.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tone is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + switches_i : in std_ulogic_vector(9 downto 0); + dv_i : in std_ulogic; + audio_i : in std_ulogic_vector(15 downto 0); + audio_o : out std_ulogic_vector(15 downto 0)); +end entity; + +architecture rtl of tone is + +begin + +audio_o <= audio_i when rising_edge(clk) and dv_i = '1'; + +end architecture rtl; |