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-rw-r--r--pnr/de1_sta/makefile14
1 files changed, 14 insertions, 0 deletions
diff --git a/pnr/de1_sta/makefile b/pnr/de1_sta/makefile
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+SIM_PROJECT_NAME = de1_sta
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined.
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+include ../makefile