pnr/de1_sta/makefile


1
2
3
4
5
6
7
8
9
10
11
12
13
14

SIM_PROJECT_NAME = de1_sta
PROJECT = $(SIM_PROJECT_NAME)

# Here the VHDL files for synthesis are defined. 
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources

# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)

FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof

include ../makefile