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authorFriedrich Beckmann <friedrich.beckmann@hs-augsburg.de>2022-05-16 18:40:52 +0200
committerFriedrich Beckmann <friedrich.beckmann@hs-augsburg.de>2022-05-16 18:40:52 +0200
commitfda13db347b69d24b7327a5b48cd2af7abfc6408 (patch)
treecec927979e53ed5c28df3ab41b487d57dc284d3a /pnr/de1_sta/makefile
parent9b7fdebd9319e3e6560ff5b3a7ad750a6957a1da (diff)
add / update de1_sta code
I modified the de1_sta demo code and added a testbench.
Diffstat (limited to 'pnr/de1_sta/makefile')
-rw-r--r--pnr/de1_sta/makefile14
1 files changed, 14 insertions, 0 deletions
diff --git a/pnr/de1_sta/makefile b/pnr/de1_sta/makefile
new file mode 100644
index 0000000..5b83d32
--- /dev/null
+++ b/pnr/de1_sta/makefile
@@ -0,0 +1,14 @@
+SIM_PROJECT_NAME = de1_sta
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined.
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+include ../makefile