2 files changed, 3 insertions, 3 deletions
diff --git a/top_simple/src/Config.scala b/top_simple/src/Config.scala
index dbfe54b..682d463 100644
--- a/top_simple/src/Config.scala
+++ b/top_simple/src/Config.scala
@@ -5,7 +5,7 @@ import spinal.core.sim._
 
 object Config {
   def spinal = SpinalConfig(
-    targetDirectory = "top_simple/gen",
+    targetDirectory = sys.props.getOrElse("spinalTargetDir", "top_simple/gen"),
     defaultConfigForClockDomains = ClockDomainConfig(
       resetActiveLevel = HIGH
     ),
diff --git a/top_simple/src/top_simple.scala b/top_simple/src/top_simple.scala
index ec43fe8..1f8756f 100644
--- a/top_simple/src/top_simple.scala
+++ b/top_simple/src/top_simple.scala
@@ -18,10 +18,10 @@ case class top_simple() extends Component {
 }
 
 // The following defines the vhdl and verilog code generation
-object verilog extends App {
+object genverilog extends App {
   Config.spinal.generateVerilog(top_simple())
 }
 
-object vhdl extends App {
+object genvhdl extends App {
   Config.spinal.generateVhdl(top_simple())
 }