diff options
| author | Friedrich Beckmann <friedrich.beckmann@tha.de> | 2024-05-10 12:28:38 +0200 |
|---|---|---|
| committer | Friedrich Beckmann <friedrich.beckmann@tha.de> | 2024-05-10 12:28:38 +0200 |
| commit | bc7d43b160864d53e7e4bbea81b29d5e8903baf4 (patch) | |
| tree | fbe7a598af34ddbc585976dfe39af253b1dfd864 /src | |
| parent | ee8d484d8531e425a06f23519fc09bbf2e1acf4e (diff) | |
add top_count
Diffstat (limited to 'src')
| -rw-r--r-- | src/cnt1sec.vhd | 16 | ||||
| -rw-r--r-- | src/cntm13.vhd | 18 | ||||
| -rw-r--r-- | src/t_top_count.vhd | 75 | ||||
| -rw-r--r-- | src/top_count.vhd | 43 |
4 files changed, 152 insertions, 0 deletions
diff --git a/src/cnt1sec.vhd b/src/cnt1sec.vhd new file mode 100644 index 0000000..a722ff9 --- /dev/null +++ b/src/cnt1sec.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity cnt1sec is + port ( + clk : in std_ulogic; + rst_n : in std_ulogic; + en_o : out std_ulogic); +end entity; + +architecture rtl of cnt1sec is +begin + +end architecture rtl; + diff --git a/src/cntm13.vhd b/src/cntm13.vhd new file mode 100644 index 0000000..9da61d4 --- /dev/null +++ b/src/cntm13.vhd @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity cntm13 is + port ( + clk : in std_ulogic; + rst_n : in std_ulogic; + up_i : in std_ulogic; + en_i : in std_ulogic; + cnt_o : out std_ulogic_vector(3 downto 0)); +end entity; + +architecture rtl of cntm13 is +begin + +end architecture rtl; + diff --git a/src/t_top_count.vhd b/src/t_top_count.vhd new file mode 100644 index 0000000..0372a94 --- /dev/null +++ b/src/t_top_count.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity t_top_count is +end entity; + +architecture beh of t_top_count is + + signal sim_clk : std_ulogic; + signal sim_rst_n : std_ulogic; + signal sim_x : std_ulogic; + signal sim_y : std_ulogic; + + signal sim_sw : std_ulogic_vector(9 downto 0); + signal sim_key : std_ulogic_vector(3 downto 0); + signal sim_ledr : std_ulogic_vector(9 downto 0); + signal sim_ledg : std_ulogic_vector(3 downto 0); + signal sim_exp : std_ulogic_vector(7 downto 0); + signal sim_hex0 : std_ulogic_vector(6 downto 0); + + signal simstop : boolean := false; + +begin + + -- Stimuli clock generator + clk_p : process + begin + sim_clk <= '0'; + wait for 10 ns; + sim_clk <= '1'; + wait for 10 ns; + if simstop then + wait; + end if; + end process; + + -- Stimuli reset generator + sim_rst_n <= '0', '1' after 55 ns; + + -- Stimuli key push + stim_p : process + begin + sim_x <= '0'; + wait until rising_edge(sim_rst_n); + for i in 0 to 5 loop + wait until falling_edge(sim_clk); + end loop; + sim_x <= '1'; + wait until falling_edge(sim_clk); + wait until falling_edge(sim_clk); + sim_x <= '0'; + wait for 200 ns; + simstop <= true; + wait; + end process ; + + -- Device under test instantiation + dut : entity work.top_count + port map( + SW => sim_sw, + KEY => sim_key, + CLOCK_50 => sim_clk, + HEX0 => sim_hex0, + EXP => sim_exp, + LEDG => sim_ledg, + LEDR => sim_ledr + ); + + -- Connect stimuli to input signals + sim_key(0) <= sim_rst_n; + sim_key(1) <= sim_x; + sim_key(3 downto 2) <= "00"; + sim_sw <= "1010000001"; + +end architecture beh;
\ No newline at end of file diff --git a/src/top_count.vhd b/src/top_count.vhd new file mode 100644 index 0000000..57c6998 --- /dev/null +++ b/src/top_count.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top_count is +port ( SW : in std_ulogic_vector(9 downto 0); + KEY : in std_ulogic_vector(3 downto 0); + CLOCK_50 : in std_ulogic; + HEX0 : out std_ulogic_vector(6 downto 0); + EXP : out std_ulogic_vector(7 downto 0); + LEDG : out std_ulogic_vector(3 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end entity; + +architecture rtl of top_count is + signal clk : std_ulogic; + signal rst_n : std_ulogic; + signal x : std_ulogic; + signal en : std_ulogic; + signal cnt : std_ulogic_vector(3 downto 0); +begin + -- Assign the inputs to signals with reasonable names + clk <= CLOCK_50; + rst_n <= KEY(0); + x <= KEY(1); + + cnt <= "0000"; + + bin2seg_inst: entity work.bin2seg + port map( + bin_i => cnt, + seg_o => HEX0 + ); + + -- Set the outputs; + EXP(7 downto 4) <= cnt; + EXP(3 downto 0) <= (3 => en, + 2 => x, + 1 => rst_n, + 0 => clk); + LEDR <= SW; + LEDG <= KEY; + +end architecture rtl;
\ No newline at end of file |