Added FIR design files for DE1 top level

3 files changed, 233 insertions, 0 deletions

diff --git a/pnr/de1_fir/de1_fir_pins.tcl b/pnr/de1_fir/de1_fir_pins.tcl
new file mode 100755
index 0000000..d64d936
--- /dev/null
+++ b/pnr/de1_fir/de1_fir_pins.tcl
@@ -0,0 +1,93 @@
+# Pin Configuration 
+set_location_assignment PIN_L1  -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY0
+# set_location_assignment PIN_L22 -to SW[0]
+# set_location_assignment PIN_L21 -to SW[1]
+# set_location_assignment PIN_M22 -to SW[2]
+# set_location_assignment PIN_V12 -to SW[3]
+# set_location_assignment PIN_W12 -to SW[4]
+# set_location_assignment PIN_U12 -to SW[5]
+# set_location_assignment PIN_U11 -to SW[6]
+# set_location_assignment PIN_M2  -to SW[7]
+# set_location_assignment PIN_M1  -to SW[8]
+# set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+# DAC Pins on GPIO Header
+set_location_assignment  PIN_C19  -to DAC_CLK_A
+set_location_assignment  PIN_D19  -to DAC_CLK_B
+set_location_assignment  PIN_C18  -to DAC_DA[0]
+set_location_assignment  PIN_F15  -to DAC_DA[10]
+set_location_assignment  PIN_E14  -to DAC_DA[11]
+set_location_assignment  PIN_G15  -to DAC_DA[12]
+set_location_assignment  PIN_H13  -to DAC_DA[13]
+set_location_assignment  PIN_D16  -to DAC_DA[1]
+set_location_assignment  PIN_C17  -to DAC_DA[2]
+set_location_assignment  PIN_D15  -to DAC_DA[3]
+set_location_assignment  PIN_D14  -to DAC_DA[4]
+set_location_assignment  PIN_F13  -to DAC_DA[5]
+set_location_assignment  PIN_C14  -to DAC_DA[6]
+set_location_assignment  PIN_F12  -to DAC_DA[7]
+set_location_assignment  PIN_G16  -to DAC_DA[8]
+set_location_assignment  PIN_E15  -to DAC_DA[9]
+set_location_assignment  PIN_P15  -to DAC_DB[0]
+set_location_assignment  PIN_G20  -to DAC_DB[10]
+set_location_assignment  PIN_E19  -to DAC_DB[11]
+set_location_assignment  PIN_F20  -to DAC_DB[12]
+set_location_assignment  PIN_D20  -to DAC_DB[13]
+set_location_assignment  PIN_N22  -to DAC_DB[1]
+set_location_assignment  PIN_N15  -to DAC_DB[2]
+set_location_assignment  PIN_N21  -to DAC_DB[3]
+set_location_assignment  PIN_J15  -to DAC_DB[4]
+set_location_assignment  PIN_G17  -to DAC_DB[5]
+set_location_assignment  PIN_H18  -to DAC_DB[6]
+set_location_assignment  PIN_H17  -to DAC_DB[7]
+set_location_assignment  PIN_G18  -to DAC_DB[8]
+set_location_assignment  PIN_E18  -to DAC_DB[9]
+set_location_assignment  PIN_P18  -to DAC_MODE
+set_location_assignment  PIN_C20  -to DAC_WRT_A
+set_location_assignment  PIN_P17  -to DAC_WRT_B
+set_location_assignment  PIN_C21  -to ADC_CLK_A
+set_location_assignment  PIN_D21  -to ADC_CLK_B
+set_location_assignment  PIN_L18  -to ADC_OEB_A
+set_location_assignment  PIN_K20  -to ADC_OEB_B
+set_location_assignment  PIN_J18  -to POWER_ON
+# ADC Pins on GPIO Header
+set_location_assignment  PIN_C22  -to ADC_DA[0]
+set_location_assignment  PIN_K21  -to ADC_DA[10]
+set_location_assignment  PIN_J19  -to ADC_DA[11]
+set_location_assignment  PIN_K22  -to ADC_DA[12]
+set_location_assignment  PIN_J20  -to ADC_DA[13]
+set_location_assignment  PIN_D22  -to ADC_DA[1]
+set_location_assignment  PIN_E21  -to ADC_DA[2]
+set_location_assignment  PIN_F21  -to ADC_DA[3]
+set_location_assignment  PIN_E22  -to ADC_DA[4]
+set_location_assignment  PIN_F22  -to ADC_DA[5]
+set_location_assignment  PIN_G21  -to ADC_DA[6]
+set_location_assignment  PIN_J21  -to ADC_DA[7]
+set_location_assignment  PIN_G22  -to ADC_DA[8]
+set_location_assignment  PIN_J22  -to ADC_DA[9]
+set_location_assignment  PIN_B13  -to ADC_DB[0]
+set_location_assignment  PIN_A19  -to ADC_DB[10]
+set_location_assignment  PIN_A20  -to ADC_DB[11]
+set_location_assignment  PIN_B19  -to ADC_DB[12]
+set_location_assignment  PIN_B20  -to ADC_DB[13]
+set_location_assignment  PIN_B14  -to ADC_DB[1]
+set_location_assignment  PIN_A15  -to ADC_DB[2]
+set_location_assignment  PIN_A16  -to ADC_DB[3]
+set_location_assignment  PIN_B15  -to ADC_DB[4]
+set_location_assignment  PIN_B16  -to ADC_DB[5]
+set_location_assignment  PIN_A17  -to ADC_DB[6]
+set_location_assignment  PIN_A18  -to ADC_DB[7]
+set_location_assignment  PIN_B17  -to ADC_DB[8]
+set_location_assignment  PIN_B18  -to ADC_DB[9]
+set_location_assignment  PIN_A13  -to ADC_OTR_A
+set_location_assignment  PIN_A14  -to ADC_OTR_B
diff --git a/pnr/de1_fir/makefile b/pnr/de1_fir/makefile
new file mode 100755
index 0000000..7a271a4
--- /dev/null
+++ b/pnr/de1_fir/makefile
@@ -0,0 +1,27 @@
+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+SIM_PROJECT_NAME = fir
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
diff --git a/src/de1_fir_structure.vhd b/src/de1_fir_structure.vhd
new file mode 100644
index 0000000..b75c3b5
--- /dev/null
+++ b/src/de1_fir_structure.vhd
@@ -0,0 +1,113 @@
+-------------------------------------------------------------------------------

+-- Module     : de1_fir

+-------------------------------------------------------------------------------

+-- Author     : Matthias Kamuf

+-- Company    : University of Applied Sciences Augsburg

+-------------------------------------------------------------------------------

+-- Description: Top-level of module de1_fir

+--              

+-------------------------------------------------------------------------------

+-- Revisions  : see end of file

+-------------------------------------------------------------------------------

+LIBRARY IEEE;

+USE IEEE.std_logic_1164.ALL;

+USE IEEE.numeric_std.ALL;

+

+ENTITY de1_fir IS

+  PORT (

+    CLOCK_50  : IN  std_ulogic;

+    KEY0      : IN  std_ulogic;

+    DAC_MODE  : OUT std_ulogic;

+    DAC_WRT_A : OUT std_ulogic;

+    DAC_WRT_B : OUT std_ulogic;

+    DAC_CLK_A : OUT std_ulogic;

+    DAC_CLK_B : OUT std_ulogic;

+    DAC_DA    : OUT std_ulogic_vector(13 DOWNTO 0);

+    DAC_DB    : OUT std_ulogic_vector(13 DOWNTO 0);

+    POWER_ON  : OUT std_ulogic;

+    ADC_CLK_A : OUT std_ulogic;

+    ADC_CLK_B : OUT std_ulogic;

+    ADC_OEB_A : OUT std_ulogic;

+    ADC_OEB_B : OUT std_ulogic;

+    ADC_DA    : IN  std_ulogic_vector(13 DOWNTO 0);

+    ADC_DB    : IN  std_ulogic_vector(13 DOWNTO 0);

+    ADC_OTR_A : IN  std_ulogic;

+    ADC_OTR_B : IN  std_ulogic;

+    LEDR      : OUT std_ulogic_vector(9 DOWNTO 0));

+END de1_fir;

+

+ARCHITECTURE structure OF de1_fir IS

+

+  COMPONENT fir IS

+    PORT (

+      clk_i    : IN  std_ulogic;

+      rst_ni   : IN  std_ulogic;

+      valid_i  : IN  std_ulogic;

+      sample_i : IN  std_ulogic_vector(13 DOWNTO 0);

+      valid_o  : OUT std_ulogic;

+      sample_o : OUT std_ulogic_vector(13 DOWNTO 0));

+  END COMPONENT fir;

+

+  -- component ports

+  SIGNAL clk                  : std_ulogic;

+  SIGNAL rst_n                : std_ulogic;

+  SIGNAL adc_a_dat, adc_b_dat : std_ulogic_vector(13 DOWNTO 0);

+

+BEGIN

+

+  filter : fir

+    PORT MAP (

+      clk_i    => clk,

+      rst_ni   => rst_n,

+      valid_i  => ,

+      sample_i => ,

+      valid_o  => ,

+      sample_o => );

+

+  -- clock and reset signal

+  clk   <= CLOCK_50;

+  rst_n <= KEY0;

+

+  -- valid and overflow indicator

+  LEDR <= valid & ADC_OTR_B & ADC_OTR_A & "0000000";

+

+  -- DAC in dual port mode

+  DAC_MODE <= '1';

+

+  DAC_WRT_A <= clk;

+  DAC_WRT_B <= clk;

+  DAC_CLK_A <= clk;

+  DAC_CLK_B <= clk;

+

+  -- DAC on board has 00000000000000 as minimum value

+  -- and              11111111111111 as maximum value

+  -- therefore the conversion has to look like this

+  --             input signed value              output DAC value

+  -- minimum     10000000000000                  00000000000000

+  -- zero        00000000000000                  10000000000000

+  -- maximum     01111111111111                  11111111111111

+

+  -- assign to DAC channels

+  DAC_DA <= "10000000000000" WHEN rst_n = '0' ELSE adc_a_dat WHEN falling_edge(clk);

+  DAC_DB <= "10000000000000" WHEN rst_n = '0' ELSE adc_b_dat WHEN falling_edge(clk);

+

+  -- ADC section

+  ADC_CLK_A <= clk;

+  ADC_CLK_B <= clk;

+  ADC_OEB_A <= '0';

+  ADC_OEB_B <= '0';

+

+  adc_a_dat <= (OTHERS => '0') WHEN rst_n = '0' ELSE ADC_DA WHEN rising_edge(clk);

+  adc_b_dat <= (OTHERS => '0') WHEN rst_n = '0' ELSE ADC_DB WHEN rising_edge(clk);

+

+  -- switch on DAC/ADC

+  POWER_ON <= '1';

+

+END structure;

+

+-------------------------------------------------------------------------------

+-- Revisions:

+-- ----------

+-- $Id:$

+-------------------------------------------------------------------------------

+