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| author | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2022-05-16 18:40:52 +0200 |
|---|---|---|
| committer | Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de> | 2022-05-16 18:40:52 +0200 |
| commit | fda13db347b69d24b7327a5b48cd2af7abfc6408 (patch) | |
| tree | cec927979e53ed5c28df3ab41b487d57dc284d3a /pnr | |
| parent | 9b7fdebd9319e3e6560ff5b3a7ad750a6957a1da (diff) | |
add / update de1_sta code
I modified the de1_sta demo code and added a testbench.
Diffstat (limited to 'pnr')
| -rw-r--r-- | pnr/de1_sta/de1_sta_pins.tcl | 15 | ||||
| -rw-r--r-- | pnr/de1_sta/makefile | 14 |
2 files changed, 29 insertions, 0 deletions
diff --git a/pnr/de1_sta/de1_sta_pins.tcl b/pnr/de1_sta/de1_sta_pins.tcl new file mode 100644 index 0000000..0389c9b --- /dev/null +++ b/pnr/de1_sta/de1_sta_pins.tcl @@ -0,0 +1,15 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] + + diff --git a/pnr/de1_sta/makefile b/pnr/de1_sta/makefile new file mode 100644 index 0000000..5b83d32 --- /dev/null +++ b/pnr/de1_sta/makefile @@ -0,0 +1,14 @@ +SIM_PROJECT_NAME = de1_sta +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile |