add / update de1_sta code

I modified the de1_sta demo code and added a testbench.

6 files changed, 142 insertions, 14 deletions

diff --git a/pnr/de1_sta/de1_sta_pins.tcl b/pnr/de1_sta/de1_sta_pins.tcl
new file mode 100644
index 0000000..0389c9b
--- /dev/null
+++ b/pnr/de1_sta/de1_sta_pins.tcl
@@ -0,0 +1,15 @@
+# Pin Configuration
+set_location_assignment PIN_L1  -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY0 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+
+
diff --git a/pnr/de1_sta/makefile b/pnr/de1_sta/makefile
new file mode 100644
index 0000000..5b83d32
--- /dev/null
+++ b/pnr/de1_sta/makefile
@@ -0,0 +1,14 @@
+SIM_PROJECT_NAME = de1_sta
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+include ../makefile
diff --git a/sim/de1_sta/makefile b/sim/de1_sta/makefile
new file mode 100644
index 0000000..5db242e
--- /dev/null
+++ b/sim/de1_sta/makefile
@@ -0,0 +1,9 @@
+PROJECT = de1_sta
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
diff --git a/sim/de1_sta/makefile.sources b/sim/de1_sta/makefile.sources
new file mode 100644
index 0000000..790072d
--- /dev/null
+++ b/sim/de1_sta/makefile.sources
@@ -0,0 +1,3 @@
+SYN_SOURCE_FILES = \
+../../src/de1_sta.vhd
+
diff --git a/src/de1_sta.vhd b/src/de1_sta.vhd
index 91a93aa..2f72da9 100644
--- a/src/de1_sta.vhd
+++ b/src/de1_sta.vhd
@@ -5,28 +5,45 @@ use ieee.numeric_std.all;
 entity de1_sta is
   port (
     CLOCK_50 : in  std_ulogic;
-    x_i      : in  unsigned(7 downto 0);
-    y_o      : out unsigned(x_i'range)
+    KEY0     : in std_ulogic;
+    LEDR     : out std_ulogic_vector(9 downto 0)
     );
 end de1_sta;
 
 architecture rtl of de1_sta is
 
-signal a,b,c,d : unsigned(x_i'range);
-signal sum : unsigned(x_i'range);
-signal clk : std_ulogic;
+function cnt_ones (x : unsigned) return integer is
+  variable cnt : integer range 0 to x'length;
+begin
+  cnt := 0;
+  for i in x'range loop
+    if x(i) = '1' then
+	   cnt := cnt + 1;
+	 end if;
+  end loop;
+  return cnt;
+end function;
+
+signal sum : unsigned(47 downto 0);
+signal clk, rst_n : std_ulogic;
+signal res, res_reg : std_ulogic;
+signal no_of_ones : integer range 0 to sum'length;
+signal no_of_ones_l, no_of_ones_u, no_of_ones_l_reg, no_of_ones_u_reg : integer range 0 to sum'length/2;
 
 begin
+res <= '1' when no_of_ones > sum'length/2 else '0';
+res_reg <= '0' when rst_n = '0' else res when rising_edge(clk);
+sum <= (others => '0') when rst_n = '0' else sum + 1 when rising_edge(clk);
+no_of_ones <= cnt_ones(sum);
+--no_of_ones <= no_of_ones_l_reg + no_of_ones_u_reg;
+LEDR <= (9 downto 1 => '0', 0 => res_reg) when rising_edge(clk);
+
+no_of_ones_u <= cnt_ones(sum(sum'high downto sum'length/2));
+no_of_ones_u_reg <= no_of_ones_u when rising_edge(clk);
+no_of_ones_l <= cnt_ones(sum(sum'length/2-1 downto 0));
+no_of_ones_l_reg <= no_of_ones_l when rising_edge(clk);
 
 clk <= CLOCK_50;
-
-sum <= a + b + c + d;
-
-y_o <= sum when rising_edge(clk);
-
-a <= x_i when rising_edge(clk);
-b <= a when rising_edge(clk);
-c <= b when rising_edge(clk);
-d <= c when rising_edge(clk);
+rst_n <= KEY0;
 
 end architecture;
diff --git a/src/t_de1_sta.vhd b/src/t_de1_sta.vhd
new file mode 100644
index 0000000..ecd4abf
--- /dev/null
+++ b/src/t_de1_sta.vhd
@@ -0,0 +1,70 @@
+--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg
+--
+--   Licensed under the Apache License, Version 2.0 (the "License");
+--   you may not use this file except in compliance with the License.
+--   You may obtain a copy of the License at
+--
+--       http://www.apache.org/licenses/LICENSE-2.0
+--
+--   Unless required by applicable law or agreed to in writing, software
+--   distributed under the License is distributed on an "AS IS" BASIS,
+--   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--   See the License for the specific language governing permissions and
+--   limitations under the License.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity t_de1_sta is
+end;
+
+architecture tbench of t_de1_sta is
+
+  component de1_sta is
+    port (
+      CLOCK_50    : in    std_ulogic;
+      KEY0        : in    std_ulogic;
+      LEDR        : out   std_ulogic_vector(9 downto 0)
+      );
+  end component;
+
+  signal clk, reset_n     : std_ulogic;
+  signal ledr             : std_ulogic_vector(9 downto 0);
+  signal key0             : std_ulogic;
+
+  signal simrun : boolean := true;
+
+begin
+
+  de1_sta_i0 : de1_sta
+    port map (
+      CLOCK_50    => clk,
+      KEY0        => reset_n,
+      LEDR        => ledr);
+
+  clock_p : process
+  begin
+    clk <= '0';
+    wait for 10 ns;
+    clk <= '1';
+    wait for 10 ns;
+    if not simrun then
+      wait;
+    end if;
+  end process clock_p;
+
+  simrun <= false after 5 ms;
+
+  reset_p : process
+  begin
+    reset_n <= '0';
+    wait for 10 ns;
+    reset_n <= '1';
+    wait;
+  end process reset_p;
+
+
+end;  -- architecture