diff options
| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /src/and2gate_equation.vhd | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'src/and2gate_equation.vhd')
| -rw-r--r-- | src/and2gate_equation.vhd | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/and2gate_equation.vhd b/src/and2gate_equation.vhd new file mode 100644 index 0000000..9c7f0f2 --- /dev/null +++ b/src/and2gate_equation.vhd @@ -0,0 +1,35 @@ +-------------------------------------------------------------------------------
+-- Module : and2gate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-input AND Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY and2gate IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ b_i : IN std_ulogic; -- data input b
+ y_o : OUT std_ulogic -- data output y
+ );
+END and2gate;
+
+ARCHITECTURE equation OF and2gate IS
+
+BEGIN
+
+ y_o <= a_i AND b_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
|