diff options
| author | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
|---|---|---|
| committer | Johann Faerber <johann.faerber@hs-augsburg.de> | 2022-03-09 09:48:43 +0100 |
| commit | a04bbf15b0f51696894e37f3e566998108aefd74 (patch) | |
| tree | 35a36178bfb2fa257b0afcddaec29868f6e4fc77 /src/invgate_equation.vhd | |
| parent | fd7c3d6c1352353f3ee2da9267308a51fd67315d (diff) | |
added basic design directory structure
Diffstat (limited to 'src/invgate_equation.vhd')
| -rw-r--r-- | src/invgate_equation.vhd | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/invgate_equation.vhd b/src/invgate_equation.vhd new file mode 100644 index 0000000..69e920e --- /dev/null +++ b/src/invgate_equation.vhd @@ -0,0 +1,34 @@ +-------------------------------------------------------------------------------
+-- Module : invgate
+-------------------------------------------------------------------------------
+-- Author : Johann Faerber
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Inverter Gate
+-- function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY invgate IS
+ PORT (a_i : IN std_ulogic; -- data input a
+ y_o : OUT std_ulogic -- data output y
+ );
+END invgate;
+
+ARCHITECTURE equation OF invgate IS
+
+BEGIN
+
+ y_o <= NOT a_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
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