add quartus synthesis for top_simple

4 files changed, 34 insertions, 3 deletions

diff --git a/top_simple/pnr/top_simple.sdc b/top_simple/pnr/top_simple.sdc
new file mode 100644
index 0000000..5ac173d
--- /dev/null
+++ b/top_simple/pnr/top_simple.sdc
@@ -0,0 +1 @@
+create_clock -period 20.000 -name CLOCK_50 CLOCK_50
\ No newline at end of file
diff --git a/top_simple/pnr/top_simple_pins.tcl b/top_simple/pnr/top_simple_pins.tcl
new file mode 100644
index 0000000..2cad3cf
--- /dev/null
+++ b/top_simple/pnr/top_simple_pins.tcl
@@ -0,0 +1,30 @@
+# assign pin locations to a quartus project
+
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
diff --git a/top_simple/src/Config.scala b/top_simple/src/Config.scala
index dbfe54b..682d463 100644
--- a/top_simple/src/Config.scala
+++ b/top_simple/src/Config.scala
@@ -5,7 +5,7 @@ import spinal.core.sim._
 
 object Config {
   def spinal = SpinalConfig(
-    targetDirectory = "top_simple/gen",
+    targetDirectory = sys.props.getOrElse("spinalTargetDir", "top_simple/gen"),
     defaultConfigForClockDomains = ClockDomainConfig(
       resetActiveLevel = HIGH
     ),
diff --git a/top_simple/src/top_simple.scala b/top_simple/src/top_simple.scala
index ec43fe8..1f8756f 100644
--- a/top_simple/src/top_simple.scala
+++ b/top_simple/src/top_simple.scala
@@ -18,10 +18,10 @@ case class top_simple() extends Component {
 }
 
 // The following defines the vhdl and verilog code generation
-object verilog extends App {
+object genverilog extends App {
   Config.spinal.generateVerilog(top_simple())
 }
 
-object vhdl extends App {
+object genvhdl extends App {
   Config.spinal.generateVhdl(top_simple())
 }