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2025-03-18add de1_dacHEADmasterFriedrich Beckmann
2025-03-18add de1_ledswFriedrich Beckmann
2023-04-17added de1_adcFriedrich Beckmann
2023-03-29matlab: add dds phase modelFriedrich Beckmann
2023-03-23makefile.ghdl - now shows errors on command lineJohann Faerber
2023-03-15added de1_sine sinewave generator for ADC/DAC boardFriedrich Beckmann
2023-03-12renamed makefile to makefile.modelsim, added makefile.ghdl and symbolic linkJohann Faerber
2022-06-15Created stub for DDS test with ADDA-board using Simulink flowMatthias Kamuf
2022-05-16add / update de1_sta codeFriedrich Beckmann
2022-05-16Added FIR design files for DE1 top levelMatthias Kamuf
2022-05-04Added source files for simple FIR filterMatthias Kamuf
2022-03-16added t_and2gate.vhd and de1_and2gate_structure.vhdJohann Faerber
2022-03-15added pnr/de1_matlab_audioJohann Faerber
2022-03-13added documentation examples in markdownJohann Faerber
2022-03-13removed sim/pwm and pnr/de1_pwmJohann Faerber
2022-03-13added sim/binto7segmentJohann Faerber
2022-03-13deleted equation within invgate_equation.vhdJohann Faerber
2022-03-09added basic design directory structureJohann Faerber
2022-03-09added ReadMe.mdJohann Faerber
2022-03-09Initial commitJohann Faerber
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