| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-03-18 | add de1_dacHEADmaster | Friedrich Beckmann | |
| 2025-03-18 | add de1_ledsw | Friedrich Beckmann | |
| 2023-04-17 | added de1_adc | Friedrich Beckmann | |
| 2023-03-29 | matlab: add dds phase model | Friedrich Beckmann | |
| 2023-03-23 | makefile.ghdl - now shows errors on command line | Johann Faerber | |
| 2023-03-15 | added de1_sine sinewave generator for ADC/DAC board | Friedrich Beckmann | |
| I added a sinewave generator based on DDS in VHDL to generate a sinewave with the ADC/DAC board. This can be used to demonstrate the Aliasing Lowpass filter. | |||
| 2023-03-12 | renamed makefile to makefile.modelsim, added makefile.ghdl and symbolic link | Johann Faerber | |
| 2022-06-15 | Created stub for DDS test with ADDA-board using Simulink flow | Matthias Kamuf | |
| 2022-05-16 | add / update de1_sta code | Friedrich Beckmann | |
| I modified the de1_sta demo code and added a testbench. | |||
| 2022-05-16 | Added FIR design files for DE1 top level | Matthias Kamuf | |
| 2022-05-04 | Added source files for simple FIR filter | Matthias Kamuf | |
| 2022-03-16 | added t_and2gate.vhd and de1_and2gate_structure.vhd | Johann Faerber | |
| 2022-03-15 | added pnr/de1_matlab_audio | Johann Faerber | |
| 2022-03-13 | added documentation examples in markdown | Johann Faerber | |
| 2022-03-13 | removed sim/pwm and pnr/de1_pwm | Johann Faerber | |
| 2022-03-13 | added sim/binto7segment | Johann Faerber | |
| 2022-03-13 | deleted equation within invgate_equation.vhd | Johann Faerber | |
| 2022-03-09 | added basic design directory structure | Johann Faerber | |
| 2022-03-09 | added ReadMe.md | Johann Faerber | |
| 2022-03-09 | Initial commit | Johann Faerber | |
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index : beckmanf/mengcom.git | |
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